DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 418

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4
Table 10.4 shows the target pins for high-impedance control and conditions to place the pins in
high-impedance state.
Table 10.4 Target Pins and Conditions for High-Impedance Control
10.4.1
If the input conditions set by ICSR1 occur on the POE0, POE1, POE3*, and POE8 pins, the high-
current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note
however, that these high-current and MTU2 pins enter high-impedance state only when general
input/output function or MTU2 function is selected for these pins.
(1)
When a change from a high to low level is input to the POE0, POE1, POE3*, and POE8 pins, the
high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state.
Figure 10.2 shows a sample timing after the level changes in input to the POE0, POE1, POE3*,
and POE8 pins until the respective pins enter high-impedance state.
Note: * This pin is supported only by the SH7125.
Rev. 5.00 Mar. 06, 2009 Page 398 of 770
REJ09B0243-0500
Pins
MTU2 high-current pins
(PE9/TIOC3B and
PE11/TIOC3D)
MTU2 high-current pins
(PE12/TIOC4A and
PE14/TIOC4C)
MTU2 high-current pins
(PE13/TIOC4B and
PE15/TIOC4D)
MTU2 channel 0 pin
(PE0/TIOC0A)
MTU2 channel 0 pin
(PE1/TIOC0B)
MTU2 channel 0 pin
(PE2/TIOC0C)
MTU2 channel 0 pin
(PE3/TIOC0D)
Falling Edge Detection
Operation
Input Level Detection Operation
Conditions
Input level detection,
output level comparison, or
SPOER setting
Input level detection,
output level comparison, or
SPOER setting
Input level detection,
output level comparison, or
SPOER setting
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Detailed Conditions
MTU2P1CZE •
((POE3F + POE1F + POE0F) +
(OSF1 • OCE1) + (MTU2CH34HIZ))
MTU2P2CZE •
((POE3F + POE1F + POE0F) +
(OSF1 • OCE1) + (MTU2CH34HIZ))
MTU2P3CZE •
((POE3F + POE1F + POE0F) + (OSF1 •
OCE1) + (MTU2CH34HIZ))
MTU2PE0ZE
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE1ZE
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE2ZE
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE3ZE
((POE8F • POE8E) + (MTU2CH0HIZ))