DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 403

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The port output enable (POE) can be used to place the high-current pins (pins multiplexed with
TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D in the MTU2) and the pins for
channel 0 of the MTU2 (pins multiplexed with TIOC0A, TIOC0B, TIOC0C, and TIOC0D) in
high-impedance state, depending on the change on POE0, POE1, POE3*, and POE8 input pins
and the output status of the high-current pins, or by modifying register settings. It can also
simultaneously generate interrupt requests.
10.1
• Each of the POE0, POE1, POE3*, and POE8 input pins can be set for falling edge, Pφ/8 × 16,
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
• High-current pins can be placed in high-impedance state when the high-current pin output
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
• Interrupts can be generated by input-level sampling or output-level comparison results.
The POE has input level detection circuits, output level comparison circuits, and a high-impedance
request/interrupt request generating circuit as shown in figure 10.1, Block Diagram of POE.
In addition to control by the POE, high-current pins can be placed in high-impedance state when
the oscillator stops or in software standby state. For details, refer to appendix A, Pin States.
Note: * The POE3 pin is supported only by the SH7125.
TIMMTU1A_020020030800
Pφ/16 × 16, or Pφ/128 × 16 low-level sampling.
state by POE0, POE1, POE3*, and POE8 pin falling-edge or low-level sampling.
levels are compared and simultaneous active-level output continues for one cycle or more.
state by modifying the POE register settings.
Features
Section 10 Port Output Enable (POE)
Rev. 5.00 Mar. 06, 2009 Page 383 of 770
REJ09B0243-0500