DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 647

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.7
17.7.1
(1) Download of On-Chip Program
(1.1) VBR setting change
(1.2) SCO download request and interrupt request
Figure 17.14 Timing of Contention between SCO Download Request and Interrupt Request
Before downloading the on-chip program, VBR must be set to H'84000000. If VBR is set to a
value other than H'84000000, the interrupt vector table is placed in the user MAT on setting
H'84000000 to VBR.
When VBR setting change conflicts with interrupt occurrence, whether the vector table before
or after VBR is changed is referenced may cause an error.
Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare
a vector table to be referenced when VBR is H'00000000 (initial value) at the start of the user
MAT.
Download of the on-chip programming/erasing program that is initiated by setting the SCO bit
in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover.
Operation when the SCO download request and interrupt request conflicts is described below.
1. Contention between SCO download request and interrupt request
2. Generation of interrupt requests during downloading
Figure 17.14 shows the timing of contention between execution of the instruction that sets
the SCO bit in FCCS to 1 and interrupt acceptance.
Ensure that interrupts are not generated during downloading that is initiated by the SCO
bit.
CPU cycle
CPU operation for instruction
that sets SCO bit to 1
Interrupt acceptance
Usage Notes
Interrupts during Programming/Erasing
(a) When the interrupt is accepted at the (n + 1) cycle or before
(b) When the interrupt is accepted at the (n + 2) cycle or later
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated.
Fetch
n
(a)
Decoding
n+1
Execution
n+2
(b)
Rev. 5.00 Mar. 06, 2009 Page 627 of 770
Execution
n+3
Execution
REJ09B0243-0500
n+4