DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 411

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
10.3.3
ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the
enable/disable of interrupts, and indicates status.
Initial value:
Bit
14 to 10 ⎯
9
8
7 to 0
Notes:
R/W:
Bit:
1.
2.
2. Can be modified only once after a power-on reset.
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Can be modified only once after a power-on reset.
Bit Name
OCE1
OIE1
⎯
Input Level Control/Status Register 3 (ICSR3)
15
R
0
-
14
R
0
-
13
Initial
value
All 0
0
0
All 0
R
0
-
R/(W)*
POE8F
12
0
1
R/W
R
R/W*
R/W
R
11
R
0
-
2
10
R
0
-
Description
Reserved
Output Short High-Impedance Enable 1
This bit specifies whether to place the pins in high-
impedance state when the OSF1 bit in OCSR1 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
Output Short Interrupt Enable 1
Reserved
These bits are always read as 0. The write value should
always be 0.
This bit enables or disables interrupt requests when the
OSF1 bit in OCSR is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
These bits are always read as 0. The write value should
always be 0.
POE8E
R/W*
9
0
2
R/W
PIE3
8
0
R
7
0
-
R
Rev. 5.00 Mar. 06, 2009 Page 391 of 770
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0243-0500
2
R
0
-
R/W*
POE8M[1:0]
1
0
2
R/W*
0
0
2