DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 224

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.3.7
The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring
data from the buffer register to the timer general register in PWM mode. The MTU2 has three
TBTM registers, one each for channels 0, 3, and 4.
Rev. 5.00 Mar. 06, 2009 Page 204 of 770
REJ09B0243-0500
Bit
7 to 3
2
1
Bit Name
—
TTSE
TTSB
Timer Buffer Operation Transfer Mode Register (TBTM)
Initial value:
Initial
Value
All 0
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies the timing for transferring data from TGRF_0
to TGRE_0 when they are used together for buffer
operation.
In channels 3 and 4, bit 2 is reserved. It is always read
as 0 and the write value should always be 0. When
using channel 0 in other than PWM mode, do not set
this bit to 1.
0: When compare match E occurs in channel 0
1: When TCNT_0 is cleared
Specifies the timing for transferring data from TGRD to
TGRB in each channel when they are used together for
buffer operation. When using channel 0 in other than
PWM mode, do not set this bit to 1.
0: When compare match B occurs in each channel
1: When TCNT is cleared in each channel
Timing Select E
Timing Select B
R
5
0
-
R
4
0
-
R
3
0
-
TTSE
R/W
2
0
TTSB
R/W
1
0
TTSA
R/W
0
0