DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 249
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 249 of 794
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9.3.25
TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer
register for the TCDR register. The TCBR register values are transferred to the TCDR register
with the transfer timing set in the TMDR register.
The initial value of TCBR is H'FFFF.
Initial value:
9.3.26
TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and
specifies the interrupt skipping count. The MTU2 has one TITCR.
Bit
7
6 to 4
3
Note:
R/W:
Bit:
Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
Bit Name
T3AEN
3ACOR[2:0] 000
T4VEN
R/W
Timer Cycle Buffer Register (TCBR)
Timer Interrupt Skipping Set Register (TITCR)
15
1
R/W
14
1
R/W
13
Initial value:
1
Initial
value
0
0
R/W
R/W:
12
1
Bit:
T3AEN
R/W
R/W
11
1
7
0
R/W
R/W
R/W
R/W
R/W
R/W
10
1
6
0
3ACOR[2:0]
Description
Enables or disables TGIA_3 interrupt skipping.
0: TGIA_3 interrupt skipping disabled
1: TGIA_3 interrupt skipping enabled
within the range from 0 to 7.*
For details, see table 9.40.
Enables or disables TCIV_4 interrupt skipping.
0: TCIV_4 interrupt skipping disabled
1: TCIV_4 interrupt skipping enabled
T3AEN
These bits specify the TGIA_3 interrupt skipping count
T4VEN
R/W
R/W
9
1
5
0
R/W
R/W
8
1
4
0
T4VEN
R/W
R/W
7
1
3
0
R/W
R/W
Rev. 5.00 Mar. 06, 2009 Page 229 of 770
6
1
2
0
4VCOR[2:0]
R/W
R/W
5
1
1
0
R/W
R/W
4
1
0
0
R/W
3
1
REJ09B0243-0500
R/W
2
1
R/W
1
1
R/W
0
1
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