DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 427

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.3.2
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal
reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset using the
RES pin.
When used to count the clock settling time for canceling a software standby, it retains its value
after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a
byte access to read WTCSR.
Note: WTCSR differs from other registers in that it is more difficult to write to. See section
Bit
7
6
11.3.3, Notes on Register Access, for details.
Bit Name
TME
WT/IT
Watchdog Timer Control/Status Register (WTCSR)
Initial value:
Initial
Value
0
0
R/W:
Bit:
TME
R/W
R/W
R/W
R/W
7
0
WT/IT
R/W
6
0
Description
Timer Enable
Starts and stops timer operation. Clear this bit to 0 when
using the WDT to revoke software standby mode
0: Timer disabled: Count-up stops and WTCNT value is
1: Timer enabled
Timer Mode Select
Selects whether to use the WDT as a watchdog timer or
an interval timer.
0: Interval timer mode
1: Watchdog timer mode
Note: If WT/IT is modified when the WDT is operating,
RSTS WOVF
R/W
retained
5
0
the up-count may not be performed correctly.
R/W
4
0
IOVF
R/W
3
0
R/W
Rev. 5.00 Mar. 06, 2009 Page 407 of 770
2
0
CKS[2:0]
R/W
1
0
R/W
0
0
REJ09B0243-0500

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