DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 415

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3.5
POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins.
Bit
7 to 4
3
2
1
Bit Name
—
MTU2PE3ZE
MTU2PE2ZE
MTU2PE1ZE
Port Output Enable Control Register 1 (POECR1)
Note:
*
Initial value:
Initial
value
All 0
0
0
0
Can be modified only once after a power-on reset.
R/W:
Bit:
R/W
R
R/W*
R/W*
R/W*
R
7
0
-
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MTU2 PE3 High-Impedance Enable
This bit specifies whether to place the PE3/TIOC1D
pin for channel 0 in the MTU2 in high-impedance
state when either POE8F or MTU2CH0HIZ bit is set
to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
MTU2 PE2 High-Impedance Enable
This bit specifies whether to place the PE2/TIOC1C
pin for channel 0 in the MTU2 in high-impedance
state when either POE8F or MTU2CH0HIZ bit is set
to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
MTU2 PE1 High-Impedance Enable
This bit specifies whether to place the PE1/TIOC1B
pin for channel 0 in the MTU2 in high-impedance
state when either POE8F or MTU2CH0HIZ bit is set
to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
R
5
0
-
R
4
0
-
R/W* R/W* R/W* R/W*
PE3ZE
MTU2
3
0
Rev. 5.00 Mar. 06, 2009 Page 395 of 770
PE2ZE
MTU2
2
0
PE1ZE
MTU2
1
0
PE0ZE
MTU2
0
0
REJ09B0243-0500