DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 475

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the EIO bit in SCSPTR is cleared to 0 and the RIE bit in SCSCR is set to 1 when the RDRF
Table 12.16 Receive Errors and Error Conditions
Receive Error
Overrun error
Framing error
Parity error
synchronization and starts reception.
After receiving these bits, the SCI carries out the following checks.
A. Parity check: The SCI counts the number of 1s in the received data and checks whether the
B. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the
C. Status check: The SCI checks whether the RDRF flag is 0 and the received data can be
If all the above checks are passed, the RDRF flag is set to 1 and the received data is stored in
SCRDR. If a receive error is detected, the SCI operates as shown in table 12.16.
Note: When a receive error occurs, subsequent reception cannot be continued. In addition,
flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in
SCSCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt
(ERI) request is generated.
count matches the even or odd parity specified by the O/E bit in the serial mode register
(SCSMR).
first is checked.
transferred from the receive shift register (SCRSR) to SCRDR.
the RDRF flag will not be set to 1 after reception; be sure to clear the error flag to 0.
Abbreviation
ORER
FER
PER
Error Condition
When the next data reception
is completed while the RDRF
flag in SCSSR is set to 1
When the stop bit is 0
When the received data does
not match the even or odd
parity specified in SCSMR
Rev. 5.00 Mar. 06, 2009 Page 455 of 770
Data Transfer
The received data is not
transferred from SCRSR to
SCRDR.
The received data is
transferred from SCRSR to
SCRDR.
The received data is
transferred from SCRSR to
SCRDR.
REJ09B0243-0500