DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 160

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4. When data access (address + data) is specified as a break condition:
7.3.6
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt
2. The values stored in BRSR and BRDR are as given below due to the kind of branch.
3. BRSR and BRDR have four pairs of queue structures. The top of queues is read first when the
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REJ09B0243-0500
When a data value is added to the break conditions, the address of an instruction that is within
two instructions of the instruction that matched the break condition is saved in the stack. At
which instruction the break occurs cannot be determined accurately.
When a delay slot instruction matches the condition, the branch destination address is saved in
the stack. If the instruction following the instruction that matches the break condition is a
branch instruction, the break may occur after the branch instruction or delay slot has finished.
In this case, the branch destination address is saved in the stack.
exception) is generated, the branch source address and branch destination address are stored in
BRSR and BRDR, respectively.
⎯ If a branch occurs due to a branch instruction, the address of the branch instruction is saved
⎯ If a branch occurs due to an interrupt or exception, the value saved in stack due to
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the
PCTE bit (in BRCR) off and on, the values in the queues are invalid.
in BRSR and the address of the branch destination instruction is saved in BRDR.
exception occurrence is saved in BRSR and the start address of the exception handling
routine is saved in BRDR.
PC Trace