DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 268

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer
Operation: The timing for transfer from buffer registers to timer general registers can be selected
in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer
operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match
(initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as
transfer timing is one of the following cases.
• When TCNT overflows (H'FFFF to H'0000)
• When H'0000 is written to TCNT during counting
• When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits
Note: TBTM must be modified only while TCNT stops.
Figure 9.19 shows an operation example in which PWM mode 1 is designated for channel 0 and
buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are
TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare
match B. The TTSA bit in TBTM_0 is set to 1.
Rev. 5.00 Mar. 06, 2009 Page 248 of 770
REJ09B0243-0500
in TCR
H'0F07
H'09FB
H'0532
H'0000
TIOCA
TGRA
TGRC
TCNT value
Figure 9.18 Example of Buffer Operation (2)
H'0532
H'0F07
H'0532
H'09FB
H'0F07
Time