DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet
DF71251AD50FPV
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DF71251AD50FPV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7125 Group, 32 SH7124 Group Hardware Manual ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The SH7125 Group and SH7124 Group RISC (Reduced Instruction Set Computer) microcomputer include a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will ...
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SH7125 Group and SH7124 Group manuals: Document Title SH7125 Group, SH7124 Group Hardware Manual SH-1/SH-2/SH-DSP Software Manual User's manuals for development tools: Document Title TM SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package V.9.00 User's Manual TM ...
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Section 1 Overview..................................................................................................1 1.1 Features of SH7125 and SH7124........................................................................................... 1 1.2 Block Diagram....................................................................................................................... 6 1.3 Pin Assignments .................................................................................................................... 7 1.4 Pin Functions ....................................................................................................................... 11 Section 2 CPU........................................................................................................17 2.1 Features................................................................................................................................ 17 2.2 Register Configuration......................................................................................................... 18 2.2.1 General Registers (Rn)............................................................................................ 19 2.2.2 ...
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Address Map ........................................................................................................................ 51 3.5 Initial State in This LSI........................................................................................................ 55 3.6 Note on Changing Operating Mode ..................................................................................... 55 Section 4 Clock Pulse Generator (CPG) ...............................................................57 4.1 Features................................................................................................................................ 57 4.2 Input/Output Pins................................................................................................................. 60 4.3 Clock Operating Mode......................................................................................................... 61 4.4 ...
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General Illegal Instructions..................................................................................... 84 5.6 Cases when Exceptions are Accepted .................................................................................. 85 5.7 Stack States after Exception Handling Ends........................................................................ 86 5.8 Usage Notes ......................................................................................................................... 88 5.8.1 Value of Stack Pointer (SP) .................................................................................... 88 5.8.2 Value of Vector Base Register ...
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Break Address Mask Register B (BAMRB) ......................................................... 124 7.2.8 Break Data Register B (BDRB) ............................................................................ 125 7.2.9 Break Data Mask Register B (BDMRB)............................................................... 126 7.2.10 Break Bus Cycle Register B (BBRB) ................................................................... 127 7.2.11 Break Control Register (BRCR) ........................................................................... ...
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Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) ................................................................ 210 9.3.12 Timer Counter (TCNT)......................................................................................... 211 9.3.13 Timer General Register (TGR) ............................................................................. 211 9.3.14 Timer Start Register (TSTR) ................................................................................ 212 9.3.15 Timer Synchronous Register (TSYR)................................................................... 214 ...
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Interrupt Signal Timing ........................................................................................ 330 9.7 Usage Notes ....................................................................................................................... 334 9.7.1 Module Standby Mode Setting ............................................................................. 334 9.7.2 Input Clock Restrictions ....................................................................................... 334 9.7.3 Caution on Period Setting ..................................................................................... 335 9.7.4 Contention between TCNT Write and Clear Operations...................................... 335 ...
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Software Port Output Enable Register (SPOER) .................................................. 393 10.3.5 Port Output Enable Control Register 1 (POECR1)............................................... 395 10.3.6 Port Output Enable Control Register 2 (POECR2)............................................... 396 10.4 Operation ........................................................................................................................... 398 10.4.1 Input Level Detection Operation .......................................................................... 398 10.4.2 Output-Level ...
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Operation ........................................................................................................................... 444 12.4.1 Overview .............................................................................................................. 444 12.4.2 Operation in Asynchronous Mode ........................................................................ 446 12.4.3 Clock Synchronous Mode (Channel 1 in the SH7124 is not Available)............... 456 12.4.4 Multiprocessor Communication Function ............................................................ 465 12.4.5 Multiprocessor Serial Data Transmission ............................................................. ...
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Range of Analog Power Supply and Other Pin Settings....................................... 502 13.7.5 Notes on Board Design ......................................................................................... 502 13.7.6 Notes on Noise Countermeasures ......................................................................... 503 Section 14 Compare Match Timer (CMT) ..........................................................505 14.1 Features.............................................................................................................................. 505 14.2 Register Descriptions ......................................................................................................... 506 ...
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Port A Port Register L (PAPRL) .......................................................................... 559 16.2 Port B ................................................................................................................................. 561 16.2.1 Register Descriptions............................................................................................ 561 16.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ........................................ 562 16.2.3 Port B Port Registers H and L (PBPRH ...
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Supplementary Information ............................................................................................... 631 17.8.1 Specifications of the Standard Serial Communications Interface in Boot Mode.. 631 17.8.2 Areas for Storage of the Procedural Program and Data for Programming............ 658 17.9 Off-Board Programming Mode.......................................................................................... 662 Section 18 RAM ..................................................................................................663 18.1 ...
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Section 21 Electrical Characteristics ...................................................................711 21.1 Absolute Maximum Ratings .............................................................................................. 711 21.2 DC Characteristics ............................................................................................................. 712 21.3 AC Characteristics ............................................................................................................. 714 21.3.1 Clock Timing ........................................................................................................ 715 21.3.2 Control Signal Timing .......................................................................................... 717 21.3.3 Multi Function Timer Pulse Unit 2 (MTU2) ...
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Features of SH7125 and SH7124 This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a ...
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Table 1.1 Features Items Specification • CPU Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture • Instruction length: 16-bit fixed length for improved code efficiency • Load-store architecture (basic operations are executed between registers) • ...
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Items Specification • Interrupt controller External interrupt pins (INTC) ⎯ SH7125: Five pins (NMI and IRQ3 to IRQ0) ⎯ SH7124: Four pins (NMI and IRQ3 to IRQ1) • On-chip peripheral interrupts: Priority level set for each module • Vector addresses: ...
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Items Specification • Multi-function timer Maximum 16 lines of pulse input/output and three lines of pulse input pulse unit 2 (MTU2) based on six channels of 16-bit timers (SH7125) • Maximum 12 lines of pulse input/output and three lines of ...
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Items Specification • 10 bits × 8 channels A/D converter (ADC) • Conversion request by external triggers or MTU2 • Two sample-and-hold function units (two channels can be sampled simultaneously) • I/O ports 37 general input/output pins and eight general ...
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Block Diagram The block diagram of this LSI is shown in figure 1.1. Internal bus controller I/O SCI CMT port (PFC) [Legend] ROM: On-chip ROM RAM: On-chip RAM UBC*: User break controller H-UDI*: User debugging interface INTC: Interrupt controller ...
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Pin Assignments PB3/IRQ1/POE1/TIC5V 50 PB2/IRQ0/POE0 51 PB1/TIC5W PF7/AN7 54 PF6/AN6 55 PF5/AN5 56 PF4/AN4 57 PF3/AN3 58 PF2/AN2 ...
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PB3/IRQ1/POE1/TIC5V 50 PB2/IRQ0/POE0 51 PB1/TIC5W PF7/AN7 54 PF6/AN6 55 PF5/AN5 56 PF4/AN4 57 PF3/AN3 58 PF2/AN2 59 PF1/AN1 60 ...
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PB3/IRQ1/POE1/TIC5V 38 PB1/TIC5W PF7/AN7 41 PF6/AN6 42 PF5/AN5 PF4/AN4 43 PF3/AN3 44 PF2/AN2 45 PF1/AN1 46 PF0/AN0 ...
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PB3/IRQ1/POE1/TIC5V 40 41 PB1/TIC5W 42 AVss 43 PF7/AN7 44 PF6/AN6 45 PF5/AN5 46 PF4/AN4 PF3/AN3 47 PF2/AN2 48 PF1/AN1 49 PF0/AN0 50 AVcc ...
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Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Classification Symbol Power supply Vcc Vss V CL Clock PLLVss EXTAL XTAL Operating mode MD1 control FWE I/O Name Function I Power supply Power supply pin Connect ...
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Classification Symbol RES System control MRES WDTOVF Interrupts NMI IRQ3 to IRQ0 (SH7125) IRQ3 to IRQ1 (SH7124) IRQOUT Multi function timer- TCLKA, pulse unit 2 (MTU2) TCLKB, TCLKC, TCLKD TIOC0A, TIOC0B, TIOC0C, TIOC0D TIOC1A, TIOC1B (only in SH7125) TIOC2A, TIOC2B ...
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Classification Symbol Multi function timer- TIOC3A, pulse unit 2 (MTU2) TIOC3B, TIOC3C, TIOC3D TIOC4A, TIOC4B, TIOC4C, TIOC4D TIC5U, TIC5V, TIC5W POE8, POE3, Port output enable POE1, POE0 (POE) (SH7125) POE8, POE1, POE0 (SH7124) Serial TXD2 to communication TXD0 interface (SCI) ...
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Classification Symbol A/D converter AVss I/O ports PA15 to PA0 (SH7125) PA9 to PA6, PA4, PA3, PA1, PA0 (SH7124) PB16, PB5, PB3 to PB1 (SH7125) PB5, PB3, PB1 (SH7124) PE15 to PE0 (SH7125) PE15 to PE8, PE3 to PE0 (SH7124) ...
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Classification Symbol ASEMD0* E10A interface ASEBRK* ASEBRKAK* [Legend]: The WDTOVF pin should not be pulled down. When absolutely necessary, pull it down through a resistor of 1 MΩ or larger. Notes: *1 This pin function is not supported on the ...
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Rev. 5.00 Mar. 06, 2009 Page 16 of 770 REJ09B0243-0500 ...
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Features • General registers: 32-bit register × 16 • Basic instructions: 62 • Addressing modes: 11 Register direct (Rn) Register indirect (@Rn) Post-increment register indirect (@Rn+) Pre-decrement register indirect (@-Rn) Register indirect with displacement (@disp:4, Rn) Index register indirect ...
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Register Configuration There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and system registers (32-bit × 4). Notes can be used as an index register in index register indirect or ...
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General Registers (Rn) There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation also used as an index register. With a number of instructions, R0 ...
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Bit Bit name Default 1 S Undefined 0 T Undefined • Global-base register (GBR) This register indicates a base address in GBR indirect addressing mode. The GBR indirect addressing mode is used for data transfer of the on-chip peripheral module ...
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System Registers There are four 32-bit system registers, designated two multiply and accumulate registers (MACH and MACL), a procedure register (PR), and program counter (PC). • Multiply and accumulate registers (MACH and MACL) This register stores the results of ...
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Data Formats 2.3.1 Register Data Format The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored ...
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Immediate Data Formats Immediate data of eight bits is placed in the instruction code. For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword and then calculated. For the TST, AND, OR, and XOR instructions, ...
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Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly in memory. Delayed Branching: Unconditional branch instructions means the ...
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Table 2.5 Access to Immediate Data Type This LSI's CPU 8-bit immediate MOV 16-bit immediate MOV.W @(disp,PC),R0 .DATA.W H'1234 32-bit immediate MOV.L .DATA.L H'12345678 Note: * Immediate data is accessed by @(disp,PC). Absolute Addresses: When data is accessed by absolute ...
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Table 2.7 Access with Displacement Type CPU in this LSI 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 .DATA.W H'1234 Note: * Immediate data is referenced by @(disp,PC). 2.4.2 Addressing Modes Table 2.8 lists addressing modes and effective address calculation methods. Table ...
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Addressing Instruction Mode Format Register @(disp:4, indirect with Rn) displacement Index @(R0, Rn) Effective address is sum of register Rn and R0 register indirect GBR indirect @(disp:8, with GBR) displacement Index GBR @(R0, indirect GBR) Effective Address Calculation Method Effective ...
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Addressing Instruction Mode Format PC relative with @(disp:8, displacement PC) PC relative disp:8 disp:12 Rev. 5.00 Mar. 06, 2009 Page 28 of 770 REJ09B0243-0500 Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added. After disp is ...
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Addressing Instruction Mode Format PC relative Rn Immediate #imm:8 #imm:8 #imm:8 2.4.3 Instruction Formats This section describes the instruction formats, and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The ...
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Table 2.9 Instruction Formats Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx m type 15 0 xxxx mmmm xxxx xxxx Rev. 5.00 Mar. 06, 2009 Page 30 of 770 REJ09B0243-0500 ...
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Instruction Format nm type 15 0 xxxx nnnn mmmm xxxx md type 15 0 xxxx xxxx mmmm dddd nd4 type 15 0 xxxx xxxx nnnn dddd nmd type 15 0 xxxx nnnn mmmm dddd Destination Source Operand Operand mmmm: register ...
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Instruction Format d type 15 0 xxxx xxxx dddd dddd d12 type 15 0 xxxx dddd dddd dddd nd8 type 15 0 xxxx nnnn dddd dddd i type 15 0 xxxx xxxx iiii iiii ni type 15 0 xxxx nnnn ...
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Instruction Set 2.5.1 Instruction Set by Type Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Kinds of Type Instruction Data transfer 5 instructions Arithmetic 21 operation instructions Op Code Function MOV Data transfer Immediate data ...
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Kinds of Type Instruction Arithmetic 21 operation instructions Logic 6 operation instructions Shift 10 instructions Rev. 5.00 Mar. 06, 2009 Page 34 of 770 REJ09B0243-0500 Op Code Function MULS Signed multiplication MULU Unsigned multiplication NEG Sign inversion NEGC Sign inversion ...
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Kinds of Type Instruction Branch 9 instructions System 11 control instructions Total Code Function BF Conditional branch, delayed conditional branch ( Conditional branch, delayed conditional branch ( BRA Unconditional branch BRAF Unconditional branch ...
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The instruction code, operation, and execution cycles of the instructions are listed in the following tables, classified by type. Instruction Instruction Code Indicated in MSB ↔ Indicated by mnemonic. LSB order. Explanation of Symbols Explanation of Symbols OP.Sz SRC, DEST ...
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Data Transfer Instructions Table 2.11 Data Transfer Instructions Instruction Operation imm → Sign extension MOV #imm,Rn → Rn (disp × PC) → Sign MOV.W @(disp,PC),Rn extension → Rn (disp × PC) → Rn MOV.L @(disp,PC),Rn ...
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Instruction Operation Rm → (R0 + Rn) MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) MOV.L Rm,@(R0,Rn) (R0 + Rm) → Sign MOV.B @(R0,Rm),Rn extension → Rn (R0 + Rm) → Sign MOV.W @(R0,Rm),Rn ...
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Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Instruction Operation → Rn ADD Rm, imm → Rn ADD #imm, → Rn, ADDC Rm,Rn Carry → ...
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Instruction Operation DMULU.L Rm,Rn Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits → Rn → else 0 → T EXTS.B Rm,Rn A ...
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Logic Operation Instructions Table 2.13 Logic Operation Instructions Instruction Operation Rn & Rm → Rn AND Rm,Rn R0 & imm → R0 AND #imm,R0 (R0 + GBR) & imm → AND.B #imm,@(R0,GBR) (R0 + GBR) ~Rm → Rn NOT ...
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Shift Instructions Table 2.14 Shift Instructions Instruction ROTL Rn ROTR Rn ROTCL Rn ROTCR Rn SHAL Rn SHAR Rn SHLL Rn SHLR Rn SHLL2 Rn SHLR2 Rn SHLL8 Rn SHLR8 Rn SHLL16 Rn SHLR16 Rn Rev. 5.00 Mar. 06, ...
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Branch Instructions Table 2.15 Branch Instructions Instruction Operation disp × → BF label PC nop Delayed branch BF/S label disp × ...
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System Control Instructions Table 2.16 System Control Instructions Instruction Operation 0 → T CLRT 0 → MACH, MACL CLRMAC Rm → SR LDC Rm,SR Rm → GBR LDC Rm,GBR Rm → VBR LDC Rm,VBR (Rm) → SR ...
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Instruction Operation MACH → Rn STS MACH,Rn MACL → Rn STS MACL,Rn PR → Rn STS PR,Rn Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 STS.L MACH,@–Rn Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 STS.L MACL,@–Rn Rn–4 → Rn, PR → ...
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Processing States The CPU has the five processing states: reset, exception handling, program execution, and power- down. Figure 2.4 shows the CPU state transition. From any state when RES = 0 Power-on reset state When internal power-on reset by ...
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Reset state The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the RES pin is high and MRES pin is low, the CPU enters the manual reset state. • Exception ...
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Rev. 5.00 Mar. 06, 2009 Page 48 of 770 REJ09B0243-0500 ...
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Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 ...
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Input/Output Pins Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Configuration Pin Name Input/Output MD1 Input FWE Input 3.3 Operating Modes 3.3.1 Mode 3 (Single Chip Mode) All ports can be used in this ...
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Address Map The address map for the operating modes are shown in figures 3.1 to 3.3. Figure 3.1 Address Map in SH7125, SH7124 (128 Kbytes Flash Memory Version) Mode 3 Single chip mode H'00000000 On-chip ROM (128 kbytes) (Flash ...
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Figure 3.2 Address Map in SH7125, SH7124 (64 Kbytes Flash Memory Version) Rev. 5.00 Mar. 06, 2009 Page 52 of 770 REJ09B0243-0500 Mode 3 Single chip mode H'00000000 On-chip ROM (64 kbytes) (Flash memory) H'0000FFFF H'00010000 Reserved area H'FFFF9FFF H'FFFFA000 ...
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Figure 3.3 Address Map in SH71251A and SH71241A (32 Kbytes Flash Memory Version) Mode 3 Single chip mode H'00000000 On-chip ROM (32 kbytes) (Flash memory) H'00007FFF H'00008000 Reserved area H'FFFF9FFF H'FFFFA000 On-chip RAM (8 kbytes) H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O ...
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Figure 3.4 Address Map in SH71250A and SH71240A (16 Kbytes Flash Memory Version) Rev. 5.00 Mar. 06, 2009 Page 54 of 770 REJ09B0243-0500 Mode 3 Single chip mode H'00000000 On-chip ROM (16 kbytes) (Flash memory) H'00003FFF H'00004000 Reserved area H'FFFF9FFF ...
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Initial State in This LSI In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section ...
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Rev. 5.00 Mar. 06, 2009 Page 56 of 770 REJ09B0243-0500 ...
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Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a bus clock (Bφ), a peripheral clock (Pφ), and a clock (MPφ) for the MTU2 module. The CPG also controls ...
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Figure 4.1 shows a block diagram of the CPG. Crystal XTAL oscillator EXTAL Oscillation stop Oscillation detection circuit stop detection Clock frequency control circuit OSCCR FRQCR [Legend] Frequency control register FRQCR: Oscillation stop detection control register OSCCR: STBCR1: Standby control ...
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The clock pulse generator blocks function as follows: PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or the EXTAL pin by 8. The multiplication ratio is fixed at ×8. Crystal Oscillator: The crystal oscillator ...
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Table 4.1 shows the operating clock for each module. Table 4.1 Operating Clock for Each Module Operating Clock Operating Module Internal clock (Iφ) CPU UBC* ROM RAM ⎯ Bus clock (Bφ) Note: * The UBC is not supported on 32 ...
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Clock Operating Mode Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Clock Operating Mode Source EXTAL input or crystal resonator The frequency of the external clock input from the EXTAL pin is multiplied by 8 ...
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Table 4.4 Frequency Division Ratios Specifiable with FRQCR FRQCR Division Ratio PLL Setting Multipli- cation Ratio Iφ Bφ Pφ ×8 1/8 1/8 1/8 1/4 1/8 1/8 1/4 1/4 1/4 1/2 1/4 1/4 1/2 1/2 1/2 1/8 1/8 1/8 1/4 1/8 ...
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Register Descriptions The CPG has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers Table 4.5 Register Configuration Register Name Frequency ...
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Initial Value Bit Bit Name ⎯ IFC[2:0] 011 BFC[2:0] 011 Rev. 5.00 Mar. 06, 2009 Page 64 of 770 REJ09B0243-0500 R/W Description R Reserved This bit is always read as 0. The ...
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Initial Value Bit Bit Name PFC[2:0] 011 ⎯ 011 MPFC[2:0] 011 R/W Description R/W Peripheral Clock (Pφ) Frequency Division Ratio Specify the division ratio of the peripheral clock (Pφ) frequency with ...
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Oscillation Stop Detection Control Register (OSCCR) OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects flag status output to an external pin. OSCCR can be accessed only in bytes. Bit: Initial value: R/W: ...
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Changing Frequency Selecting division ratios for the frequency divider can change the frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). This is controlled by software through the frequency control register (FRQCR). ...
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Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.6.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.6. ...
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Table 4.7 Crystal Resonator Characteristics Frequency (MHz) Rs Max. (Ω) (Reference Values) C Max. (pF) (Reference Values 4.6.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the ...
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Function for Detecting Oscillator Stop This CPG detects a stop in the clock input if any system abnormality halts the clock supply. When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit ...
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Usage Notes 4.8.1 Note on Crystal Resonator A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are ...
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A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Separate the PLL power lines (PLLVss) and the system power lines (Vcc, Vss) at the board power supply source, and be sure to insert bypass ...
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Section 5 Exception Handling 5.1 Overview 5.1.1 Types of Exception Handling and Priority Exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exceptions are detected ...
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Exception Handling Operations The exceptions are detected and the exception handling starts according to the timing shown in table 5.2. Table 5.2 Timing for Exception Detection and Start of Exception Handling Exception Reset Power-on reset Manual reset Address error ...
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Exception Handling Vector Table Before exception handling starts, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception handling routines. (The reset exception handling table holds the initial ...
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Exception Handling Source Interrupt IRQ0 (SH7125) IRQ1 IRQ2 IRQ3 (Reserved for system use) 2 On-chip peripheral module* Notes: 1. Reserved on the 32 Kbyte (SH71251A and SH71241A) and 16 Kbyte (SH71250A and SH71240A) versions. 2. For details on the vector ...
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Resets 5.2.1 Types of Resets Resets have priority over any exception source. There are two types of resets: power-on resets and manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In ...
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The values fetched from the exception handling vector table are set in PC and SP, then the program starts. Be certain to always perform power-on reset exception handling when turning the system power on. Power-On Reset by WDT: When ...
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Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Instruction ...
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Address Error Exception Source When an address error exception is generated, the bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. The CPU operates as follows: 1. The ...
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Interrupts 5.4.1 Interrupt Sources Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Type NMI User break* IRQ On-chip peripheral module Note: * ...
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Interrupt Priority The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception handling according to the results. The priority of interrupts is expressed as priority ...
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Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by ...
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Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception handling starts after the ...
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Cases when Exceptions are Accepted When an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in table ...
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Stack States after Exception Handling Ends The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Address error (when the instruction that caused an exception is placed in ...
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Types Illegal slot instruction General illegal instruction Stack State Address of → SP delayed branch instruction SR Address of → SP general illegal instruction SR Rev. 5.00 Mar. 06, 2009 Page 87 of 770 32 bits 32 bits 32 bits ...
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Usage Notes 5.8.1 Value of Stack Pointer (SP) The SP value must always be a multiple not, an address error will occur when the stack is accessed during exception handling. 5.8.2 Value of Vector ...
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Notes on Slot Illegal Instruction Exception Handling Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. • Conventional SH-2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the ...
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Rev. 5.00 Mar. 06, 2009 Page 90 of 770 REJ09B0243-0500 ...
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Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features • 16 levels of interrupt priority • NMI noise canceller function • Occurrence of interrupt can ...
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Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRQ0 *1 IRQ1 IRQ2 IRQ3 *2 (Interrupt request) UBC (Interrupt request) WDT (Interrupt request) CMT (Interrupt request) MTU2 (Interrupt request) A/D (Interrupt request) SCI (Interrupt request) POE [Legend] UBC: ...
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Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin Abbr. I/O Function NMI Input Input of non-maskable interrupt request signal IRQ0 to ...
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Register Descriptions The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers. Table 6.2 Register Configuration Register Name ...
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Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level on the NMI pin. Bit ...
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IRQ Control Register (IRQCR) IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input pins IRQ0 to IRQ3. Bit Initial value ...
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Initial Value Bit Bit Name 3 IRQ11S 0 2 IRQ10S 0 1 IRQ01S 0 0 IRQ00S 0 R/W Description R/W IRQ1 Sense Select R/W Set the interrupt request detection mode for pin IRQ1. 00: Interrupt request is detected at the ...
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IRQ Status register (IRQSR) IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to IRQ3 and the status of interrupt request. Bit Initial value: ...
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Initial Value Bit Bit Name 3 IRQ3F 0 R/W Description R/W Indicates the status of an IRQ3 interrupt request. • When level detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing condition] Driving pin IRQ3 high ...
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Initial Value Bit Bit Name 2 IRQ2F 0 1 IRQ1F 0 Rev. 5.00 Mar. 06, 2009 Page 100 of 770 REJ09B0243-0500 R/W Description R/W Indicates the status of an IRQ2 interrupt request. • When level detection mode is selected 0: ...
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Initial Value Bit Bit Name 0 IRQ0F 0 Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low. 6.3.4 Interrupt Priority Registers A ...
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Initial Value Bit Bit Name IPR[15:12] 0000 IPR[11:8] 0000 Rev. 5.00 Mar. 06, 2009 Page 102 of 770 REJ09B0243-0500 R/W Description R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 ...
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Initial Value Bit Bit Name IPR[7:4] 0000 IPR[3:0] 0000 Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by ...
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Interrupt Sources 6.4.1 External Interrupts There are four types of interrupt sources: User break, NMI, IRQ, and on-chip peripheral modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 16 the highest). Giving an ...
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Level IRQn pins detection Edge detection RESIRQn (Acceptance of IRQn interrupt/ writing 0 after reading IRQnF = 1) Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated ...
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Interrupt Exception Handling Vector Table Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. Individual interrupt sources are allocated to different vector numbers and vector table address offsets. Vector table addresses are calculated ...
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Table 6.3 Interrupt Exception Handling Vectors and Priorities Interrupt Source Name User break External pin NMI IRQ0 (only SH7125) 64 IRQ1 IRQ2 IRQ3 MTU2_0 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 TGIE_0 TGIF_0 MTU2_1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 MTU2_2 TGIA_2 TGIB_2 TCIV_2 ...
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Interrupt Source Name MTU2_4 TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 MTU2_5 TGIU_5 TGIV_5 TGIW_5 POE (MTU2) OEI1 OEI3 CMT_0 CMI_0 CMT_1 CMI_1 WDT ITI A/D_0 and ADI_0 A/D_1 ADI_1 SCI_0 ERI_0 RXI_0 TXI_0 TEI_0 SCI_1 ERI_1 RXI_1 TXI_1 TEI_1 SCI_2 ERI_2 ...
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Interrupt Operation 6.6.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects ...
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Notes: The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that ...
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Program execution state No Interrupt? Yes No User break? Yes NMI? Yes ≤ Yes level 14? No Yes 1 3 IRQOUT = low * * Save SR to stack Save PC to stack Copy interrupt level to ...
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Stack after Interrupt Exception Handling Figure 6.4 shows the stack after interrupt exception handling. Address 4n – – Notes the start address of the next instruction (instruction at the return address) after ...
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Table 6.4 Interrupt Response Time Item NMI 1 × Icyc + 2 × Interrupt priority decision and comparison with mask Pcyc bits in SR Wait for completion of X (≥ 0) sequence currently being executed by CPU 8 × Icyc ...
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Usage Note 6.8.1 Clearing Interrupt Source Flags The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag ...
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Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break ...
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Figure 7.1 shows a block diagram of the UBC. LDB Access IDB IAB control CPU state signals [Legend] BBRA: Break bus cycle register A BARA: Break address register A BAMRA: Break address mask register A BDRA: Break data register A ...
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Register Descriptions The user break controller has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 7.1 Register Configuration Register Name Break address register A Break ...
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Break Address Register A (BARA) BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 ...
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Initial Value Bit Bit Name BAMA31 to All 0 BAMA 0 7.2.3 Break Bus Cycle Register A (BBRA) BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle ...
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Initial Value Bit Bit Name 7, 6 CDA[1: IDA[1: RWA[1: SZA[1:0] 00 [Legend] x: Don't care. Rev. 5.00 Mar. 06, 2009 Page 120 of 770 REJ09B0243-0500 R/W Description R/W L Bus ...
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Break Data Register A (BDRA) BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select one of two data buses for break condition A. Bit BDA31 BDA30 BDA29 BDA28 BDA27 ...
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Break Data Mask Register A (BDMRA) BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data specified by BDRA. Bit BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 ...
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Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1 and CDB0 in BBRB select one of the two address buses for break ...
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Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 ...
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Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register. The control bits CDB1 and CDB0 in BBRB select one of the two data buses for break condition B. Bit BDB31 BDB30 BDB29 BDB28 ...
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Break Data Mask Register B (BDMRB) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 ...
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Break Bus Cycle Register B (BBRB) BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, ...
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Initial Value Bit Bit Name 5, 4 IDB[1: RWB[1: SZB[1:0] 0 [Legend] x: Don't care. Rev. 5.00 Mar. 06, 2009 Page 128 of 770 REJ09B0243-0500 R/W Description R/W Instruction Fetch/Data Access Select B Select ...
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Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition break is set before or after instruction execution. 3. Specify whether ...
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Initial Value Bit Bit Name ⎯ UBIDA 0 ⎯ SCMFCA 0 14 SCMFCB 0 13 SCMFDA 0 Rev. 5.00 Mar. 06, 2009 Page 130 of 770 REJ09B0243-0500 R/W Description R Reserved This bit is ...
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Initial Value Bit Bit Name 12 SCMFDB 0 11 PCTE 0 10 PCBA 0 ⎯ All 0 7 DBEA 0 6 PCBB 0 R/W Description R/W I Bus Cycle Condition Match Flag B When the I bus cycle ...
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Initial Value Bit Bit Name 5 DBEB 0 ⎯ SEQ 0 ⎯ All 0 0 ETBE 0 Rev. 5.00 Mar. 06, 2009 Page 132 of 770 REJ09B0243-0500 R/W Description R/W Data Break Enable B Selects ...
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Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The 12 maximum number is 2 ...
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Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This ...
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Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This ...
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Operation 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break address registers (BARA or BARB). The masked ...
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Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word, longword, or not including the operand size is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether ...
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Table 7.2 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address Compared Longword Compares break address register bits address bus bits Word Compares break address register bits ...
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Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if ...
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When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break ...
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Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1) • Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = ...
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B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word After an instruction with address H'00037226 is executed, a user break occurs before an instruction with address H'0003722E is executed. ...
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B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user ...
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Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not ...
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Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) • Register specifications BARA = H'00314154, BAMRA = H'00000000, BBRA = H'0194, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'01A9, BDRB = ...
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Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the ...
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Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a SLEEP instruction or ...
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Rev. 5.00 Mar. 06, 2009 Page 148 of 770 REJ09B0243-0500 ...
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Section 8 Bus State Controller (BSC) The bus state controller (BSC) controls data transmission and reception between the internal buses (L bus, I bus, and peripheral bus) and also controls the CPU’s access to the on-chip FLASH, on- chip RAM, ...
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Access to on-chip Peripheral I/O Register The on-chip peripheral I/O register is accessed by the bus state controller (BSC) as described in table 8.2. Table 8.2 Connection Bus Width of on-chip Peripheral Module and the Number of Access Cycles ...
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Iclk L bus Bclk I bus Pclk Peripheral bus Figure 8.1 Timing of Write Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:1:1) Figure 8.2 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk = 4:4:1. ...
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Iclk ≥ Bclk ≥ Pclk. In the case shown in figure 8.3, where and the period required for access by the CPU is 3 × Iclk + 2 × Bclk ...
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Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels. 9.1 Features • Maximum 16 (SH7125 (SH7124) pulse input/output lines and three pulse ...
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Table 9.1 MTU2 Functions Item Channel 0 Count clock MPφ/1 MPφ/4 MPφ/16 MPφ/64 TCLKA TCLKB TCLKC TCLKD General registers TGRA_0 TGRB_0 TGRE_0 General registers/ TGRC_0 buffer registers TGRD_0 TGRF_0 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D Counter clear TGR function compare ...
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Item Channel 0 Phase counting — mode √ Buffer operation Dead time — compensation counter function A/D converter start TGRA_0 trigger compare match or input capture TGRE_0 compare match Channel 1 Channel 2 Channel 3 √ √ — √ — ...
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Item Channel 0 Interrupt sources 7 sources • Compare match or input capture 0A • Compare match or input capture 0B • Compare match or input capture 0C • Compare match or input capture 0D • Compare match 0E • ...
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Item Channel 0 A/D converter start — request delaying function Interrupt skipping — function [Legend] √ Possible : —: Not possible Notes: 1. This pin is supported only by the SH7125. 2. Input capture is supported only by the SH7125. ...
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Figure 9.1 shows a block diagram of the MTU2. Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Input pins Channel 5: TIC5U TIC5V TIC5W Clock input Internal clock: MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 ...
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Input/Output Pins Table 9.2 Pin Configuration Channel Pin Name I/O Common TCLKA Input External clock A input pin TCLKB Input External clock B input pin TCLKC Input External clock C input pin TCLKD Input External clock D input pin ...
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Register Descriptions The MTU2 has the following registers. For details on register addresses and register states during each process, see section 20, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added ...
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Register Name Timer subcounter Timer cycle buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 Timer interrupt skipping set register Timer interrupt skipping counter Timer ...
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Register Name Timer waveform control register Timer start register Timer synchronous register Timer read/write enable register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer ...
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Register Name Timer counter_1 Timer general register A_1 Timer general register B_1 Timer input capture control register Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 ...
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Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels and three (TCRU_5, TCRV_5, ...
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Table 9.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Bit 7 Bit 6 Channel CCLR2 CCLR1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to ...
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Table 9.6 TPSC0 to TPSC2 (Channel 0) Bit 2 Bit 1 Channel TPSC2 TPSC1 Table 9.7 TPSC0 to TPSC2 (Channel 1) Bit 2 Bit 1 Channel TPSC2 TPSC1 ...
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Table 9.8 TPSC0 to TPSC2 (Channel 2) Bit 2 Bit 1 Channel TPSC2 TPSC1 Note: This setting is ignored when channel phase counting mode. Table 9.9 TPSC0 to TPSC2 (Channels ...
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Table 9.10 TPSC1 and TPSC0 (Channel 5) Bit 1 Bit 0 Channel TPSC1 TPSC0 Note: Bits are reserved in channel 5. These bits are always read as 0. The write ...
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Initial Bit Bit Name Value 5 BFB 0 4 BFA MD[3:0] 0000 R/W Description R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used ...
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Table 9.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 Bit 2 Bit 1 MD3 MD2 MD1 [Legend] x: Don't care Notes: 1. ...
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Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 ...
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TIORL_0, TIORL_3, TIORL_4 Bit: Initial value: R/W: Initial Bit Bit Name Value IOD[3:0] 0000 IOC[3:0] 0000 • TIORU_5, TIORV_5, TIORW_5 Bit name: Initial value: R/W: Initial Bit Bit Name Value ⎯ ...
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Table 9.12 TIORH_0 (Channel 0) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 ...
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Table 9.13 TIORL_0 (Channel 0) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 ...
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Table 9.14 TIOR_1 (Channel 1) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 ...
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Table 9.15 TIOR_2 (Channel 2) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] ...
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Table 9.16 TIORH_3 (Channel 3) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] ...
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Table 9.17 TIORL_3 (Channel 3) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 [Legend] ...
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Table 9.18 TIORH_4 (Channel 4) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] ...
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Table 9.19 TIORL_4 (Channel 4) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 [Legend] ...