DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 478

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 12.9 shows a sample flowchart for initializing the SCI.
Rev. 5.00 Mar. 06, 2009 Page 458 of 770
REJ09B0243-0500
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to
Set the PFC for the external pins to be
Set the RIE, TIE, TEIE, and MPIE bits
Set CKE1 and CKE0 bits in SCSCR
Set TE and RE bits of SCSCR to 1
TE and RE bits in SCSCR to 0*
Clear RIE, TIE, TEIE, MPIE,
Set data transfer format in
used (SCK, TXD, RXD)
0 or set to 1 simultaneously.
(TE and RE bits are 0)
1-bit interval elapsed?
Set value in SCBRR
Start initialization
<Transfer starts>
in SCSCR
SCSMR
Figure 12.9 Sample Flowchart for SCI Initialization
Yes
Wait
No
[4]
[5]
[2]
[3]
[1]
[1]
[2]
[3]
[4]
[5]
Set the clock selection in SCSCR.
Set the data transfer format in SCSMR.
Write a value corresponding to the bit rate to
SCBRR. Not necessary if an external clock is
used.
Set PFC of the external pin used. Set RXD
input during receiving and TXD output during
transmitting. Set SCK input/output according
to contents set by CKE1 and CKE0.
Set the TE bit or RE bit in SCR to 1.* Also
make settings of the RIE, TIE, TEIE, and
MPIE bits. At this time, the TXD, RXD, and
SCK pins are ready to be used. The TXD pin
is in a mark state during transmitting. When
synchronous clock output (clock master) is
set during receiving in clock synchronous
mode, outputting clocks from the SCK pin
starts.