DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 477

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first)
to the MSB (last). After output of the MSB, the communication line remains in the state of the
MSB. In clock synchronous mode, the SCI transmits or receives data by synchronizing with the
rising edge of the serial clock.
(1)
The data length is fixed at eight bits. No parity bit can be added.
(2)
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source,
see table 12.14.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. When only reception is performed, the
synchronous clock continues to be output until an overrun error occurs or the RE bit is cleared to
0. For the reception of n characters, select the external clock as the clock source. If the internal
clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the same
time as receiving the n characters of data.
(3)
SCI Initialization (Clock Synchronous Mode):
Before transmitting, receiving, or changing the mode or communication format, the software must
clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI.
Clearing TE to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR).
Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive
data register (SCRDR), which retain their previous contents.
Communication Format
Clock
Transmitting and Receiving Data
Rev. 5.00 Mar. 06, 2009 Page 457 of 770
REJ09B0243-0500