DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 409
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 409 of 794
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Bit
8
7, 6
5, 4
3, 2
Bit Name
PIE1
POE3M[1:0]
⎯
POE1M[1:0]
Initial
value
0
00
All 0
00
R/W
R/W
R/W*
R/W*
R/W*
2
2
2
Description
POE3 mode 1, 0
(Supported only by the SH7125. Write 00 to these bits in
the SH7124.)
These bits select the input mode of the POE3 pin.
10: Accept request when POE3 input has been sampled
11: Accept request when POE3 input has been sampled
Reserved
These bits are always read as 0. The write value should
always be 0.
POE1 mode 1, 0
These bits select the input mode of the POE1 pin.
10: Accept request when POE1 input has been sampled
11: Accept request when POE1 input has been sampled
Port Interrupt Enable 1
This bit enables/disables interrupt requests when any one
of the POE0F to POE3F bits of the ICSR1 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
for 16 Pφ/16 clock pulses and all are low level.
for 16 Pφ/128 clock pulses and all are low level.
for 16 Pφ/8 clock pulses and all are low level.
for 16 Pφ/16 clock pulses and all are low level.
for 16 Pφ/128 clock pulses and all are low level.
Rev. 5.00 Mar. 06, 2009 Page 389 of 770
REJ09B0243-0500
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