DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 135

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
7.1
The UBC has the following features:
1. The following break comparison conditions can be set.
• Address
• Data
• Bus cycle
• Read/write
• Operand size
2. A user-designed user-break condition interrupt exception processing routine can be run.
3. In an instruction fetch cycle, it can be selected that a user-break is set before or after an
4. Maximum repeat times for the break condition (only for channel B): 2
5. Four pairs of branch source/destination buffers.
Note: * The user break controller is not supported on the 32 Kbyte (SH71251A and
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
Comparison bits are maskable in 1-bit units.
One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected.
32-bit maskable.
One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected.
Instruction fetch or data access
Byte, word, and longword
instruction is executed.
Features
SH71241A) and 16 Kbyte (SH71250A and SH71240A) versions.
Section 7 User Break Controller (UBC)
Rev. 5.00 Mar. 06, 2009 Page 115 of 770
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