DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 93

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.1
5.1.1
Exception handling is started by four sources: resets, address errors, interrupts and instructions and
have the priority, as shown in table 5.1. When several exceptions are detected at once, they are
processed according to the priority.
Table 5.1
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
Exception
Reset
Interrupt
Address error
Instruction
Address error
Interrupt
2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,
3. The user break interrupt is not generated on the 32 Kbyte (SH71251A and SH71241A)
Overview
Types of Exception Handling and Priority
BRAF.
TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.
and 16 Kbyte (SH71250A and SH71240A) versions.
Types of Exceptions and Priority
Exception Source
Power-on reset
Manual reset
User break (break before instruction execution)*
CPU address error (instruction fetch)
General illegal instructions (undefined code)
Illegal slot instruction (undefined code placed immediately after a
delayed branch instruction*
Trap instruction (TRAPA instruction)
CPU address error (data access)
User break (break after instruction execution or operand break)*
NMI
IRQ
On-chip peripheral modules
Section 5 Exception Handling
1
or instruction that changes the PC value*
Rev. 5.00 Mar. 06, 2009 Page 73 of 770
3
3
REJ09B0243-0500
2
)
Priority
High
Low

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