DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 642

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(3) Erasing Procedure in User Program Mode
Rev. 5.00 Mar. 06, 2009 Page 622 of 770
REJ09B0243-0500
The procedures for download, initialization, and erasing are shown in figure 17.12.
The details of the erasing procedure are described below. The procedure program must be
executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in
on-chip RAM.
Specify 1/4 (initial value) as the frequency division ratios of an internal clock (Iφ), a bus clock
(Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR).
After the programming/erasing program has been downloaded and the SCO bit is cleared to 0,
the setting of the frequency control register (FRQCR) can be changed to the desired value. For
the downloaded on-chip program area, see the RAM map for programming/erasing in figure
17.10.
JSR FTDAR setting + 32
set download destination
Select on-chip program
Start erasing procedure
to be downloaded and
Set the FPEFEQ and
After clearing VBR,
FUBRA parameters
execute download
Set FKEY to H'A5
set SCO to 1 and
Clear FKEY to 0
FPFR = 0 ?
Initialization
DPFR = 0?
by FTDAR
program
1
Yes
Yes
Initialization error processing
Download error processing
No
No
(3.1)
Figure 17.12 Erasing Procedure
No
JSR FTDAR setting + 16
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
Required block
FPFR = 0 ?
End erasing
completed?
erasing is
Erasing
1
Yes
Yes
Clear FKEY and erasing
No
error processing
(3.2)
(3.3)
(3.4)
(3.5)
(3.6)

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