DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 32

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 5.00 Mar. 06, 2009 Page 12 of 770
REJ09B0243-0500
Classification
System control
Interrupts
Multi function timer-
pulse unit 2 (MTU2)
Symbol
RES
MRES
WDTOVF
NMI
IRQ3 to IRQ0
(SH7125)
IRQ3 to IRQ1
(SH7124)
IRQOUT
TCLKA,
TCLKB,
TCLKC,
TCLKD
TIOC0A,
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
TIOC1B
(only in
TIOC2A,
TIOC2B
(only in
SH7125)
SH7125)
I/O
I
I
O
I
I
O
I
I/O
I/O
I/O
Name
Power-on reset
Manual reset
Watchdog timer
overflow
Non-maskable
interrupt
Interrupt requests
3 to 0
Interrupt request
output
MTU2 timer clock
input
MTU2 input
capture/output
compare
(channel 0)
MTU2 input
capture/output
compare
(channel 1)
MTU2 input
capture/output
compare
(channel 2)
Function
When low, this LSI enters the power-
on reset state.
When low, this LSI enters the
manual reset state.
Output signal for the watchdog timer
overflow
If this pin needs to be pulled down,
use the resistor larger than
1 MΩ to pull this pin down.
Non-maskable interrupt request pin
Fix to high or low level when not in
use.
Maskable interrupt request pins
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release
state.
External clock input pins for the timer
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins
The TGRA_1 to TGRB_1 input
capture input/output compare
output/PWM output pins
The TGRA_2 to TGRB_2 input
capture input/output compare
output/PWM output pins

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