DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 410

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
10.3.2
OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
Initial value:
Rev. 5.00 Mar. 06, 2009 Page 390 of 770
REJ09B0243-0500
Bit
1, 0
Bit
15
Notes:
R/W:R/(W)*
Bit:
1.
2.
2. Can be modified only once after a power-on reset.
Bit Name
POE0M[1:0]
OSF1
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Can be modified only once after a power-on reset.
Output Level Control/Status Register 1 (OCSR1)
Bit Name
OSF1
15
0
1
14
R
0
-
13
Initial
value
0
R
0
-
Initial
value
00
12
R
0
-
R/W
R/W*
R/W
R/(W)*
11
R
0
-
2
10
R
0
-
1
Description
POE0 mode 1, 0
These bits select the input mode of the POE0 pin.
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
10: Accept request when POE0 input has been sampled
11: Accept request when POE0 input has been sampled
Description
Output Short Flag 1
This flag indicates that any one of the three pairs of
MTU2 2-phase outputs to be compared has
simultaneously become an active level.
[Clearing condition]
•
[Setting condition]
•
R/W*
OCE1
9
0
By writing 0 to OSF1 after reading OSF1 = 1
When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
for 16 Pφ/16 clock pulses and all are low level.
for 16 Pφ/128 clock pulses and all are low level.
for 16 Pφ/8 clock pulses and all are low level.
2
OIE1
R/W
8
0
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
R
2
0
-
R
1
0
-
R
0
0
-