DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 596

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.4.2
The port F data register L (PFDRL) is a 16-bit read-only register that stores port F data. Bits
PF7DR to PF0DR correspond to pins PF7 to PF0 (multiplexed functions omitted here) in the
SH7125 and SH7124.
Any value written into these bits is ignored, and there is no effect on the state of the pins. When
any of the bits are read, the pin state rather than the bit value is read directly. However, when an
A/D converter analog input is being sampled, values of 1 are read. Table 16.8 summarizes port F
data register L read/write operations.
• PFDRL (SH7125, SH7124)
Initial value:
Table 16.8 Port F Data Register L (PFDRL) Read/Write Operations
• PFDRL Bits 7 to 0
Rev. 5.00 Mar. 06, 2009 Page 576 of 770
REJ09B0243-0500
Bit
15 to 8
7
6
5
4
3
2
1
0
Pin Function
General input
ANn input
R/W:
Bit:
Port F Data Register L (PFDRL)
15
R
0
-
Bit Name
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
14
R
0
-
13
R
0
-
Initial
Value
All 0
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
12
R
0
-
11
R
0
-
R/W
R
Read
Pin state
1
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
See table 16.8.
R
9
0
-
R
8
0
-
PF7
DR
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
R
7
*
PF6
DR
R
6
*
PF5
DR
R
5
*
PF4
DR
R
4
*
PF3
DR
R
3
*
PF2
DR
R
2
*
PF1
DR
R
1
*
PF0
DR
R
0
*

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