DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 189
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 189 of 794
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Bit
5
4
3 to 0
Bit Name
BFB
BFA
MD[3:0]
Initial
Value
0
0
0000
R/W
R/W
R/W
R/W
Description
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare do not
take place in modes other than complementary PWM
mode, but compare match with TGRD occurs in
complementary PWM mode. Since the TGFD flag will
be set if a compare match occurs during Tb interval in
complementary PWM mode, the TGIED bit in timer
interrupt enable register 3/4 (TIER_3/4) should be
cleared to 0.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare do not
take place in modes other than complementary PWM
mode, but compare match with TGRD occurs in
complementary PWM mode. Since the TGFD flag will
be set if a compare match occurs during Tb interval in
complementary PWM mode, the TGIED bit in timer
interrupt enable register 3/4 (TIER_3/4) should be
cleared to 0.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
These bits are used to set the timer operating mode.
See table 9.11 for details.
Buffer Operation B
Buffer Operation A
Modes 0 to 3
Rev. 5.00 Mar. 06, 2009 Page 169 of 770
REJ09B0243-0500
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