DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 632

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) SCI Interface Setting by Host
Table 17.7 Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Rate of
Note: The internal clock division ratio of ×1/3 is not supported in boot mode.
Rev. 5.00 Mar. 06, 2009 Page 612 of 770
REJ09B0243-0500
Host Bit Rate
9,600 bps
19,200 bps
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-
communication data (H'00), which is transmitted consecutively by the host. The SCI
transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit
rate of transmission by the host by means of the measured low period and transmits the bit
adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment
end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When
reception is not executed normally, boot mode is initiated again (reset) and the operation
described above must be executed. The bit rate between the host and this LSI is not matched
because of the bit rate of transmission by the host and system clock frequency of this LSI. To
operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200
bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI is shown in table 17.7. Boot mode must be initiated in the range of this
system clock. Note that the internal clock division ratio of ×1/3 is not supported in boot mode.
This LSI
Figure 17.7 Automatic Adjustment Operation of SCI Bit Rate
Peripheral Clock (Pφ) Frequency Which Can Automatically Adjust LSI's
Bit Rate
20 to 25 MHz
20 to 25 MHz
Start
bit
D0
Measure low period (9 bits) (data is H'00)
D1
D2
D3
D4
D5
D6
D7
Stop bit
High period of
at least 1 bit