DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 447
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 447 of 794
- Download datasheet (5Mb)
Bit
4
Bit Name
FER
Initial
value
0
R/W
R/(W)* Framing Error
Description
Indicates that a framing error occurred during data
reception in asynchronous mode, causing abnormal
termination.
0: Indicates that reception is in progress or was
[Clearing conditions]
•
•
1: Indicates that a framing error occurred during
[Setting condition]
•
Notes: 1. The FER flag is not affected and retains
completed successfully*
reception
By a power-on reset or in standby mode
When 0 is written to FER after reading FER = 1
When the SCI founds that the stop bit at the end
of the received data is 0 after completing
reception*
2. In 2-stop-bit mode, only the first stop bit is
its previous value when the RE bit in
SCSCR is cleared to 0.
checked for a value to 1; the second stop
bit is not checked. If a framing error
occurs, the receive data is transferred to
SCRDR but the RDRF flag is not set.
Subsequent serial reception cannot be
continued while the FER flag is set to 1.
2
Rev. 5.00 Mar. 06, 2009 Page 427 of 770
1
REJ09B0243-0500
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