DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 257

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4
9.4.1
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, cycle counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Always select MTU2 external pins set function using the pin function controller (PFC).
Counter Operation:
When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set
to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a
free-running counter, periodic counter, for example.
1. Example of Count Operation Setting Procedure
Figure 9.4 shows an example of the count operation setting procedure.
Operation
Basic Functions
Select counter clearing
Select output compare
Start count operation
Select counter clock
Operation selection
<Periodic counter>
Periodic counter
Set period
Figure 9.4 Example of Counter Operation Setting Procedure
register
source
[1]
[2]
[3]
[4]
[5]
<Free-running counter>
Free-running counter
Start count operation
[5]
Rev. 5.00 Mar. 06, 2009 Page 237 of 770
[1] Select the counter clock
[2] For periodic counter
[3] Designate the TGR
[4] Set the periodic counter
[5] Set the CST bit in TSTR to
with bits TPSC2 to TPSC0
in TCR. At the same time,
select the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
operation, select the TGR
to be used as the TCNT
clearing source with bits
CCLR2 to CCLR0 in TCR.
selected in [2] as an output
compare register by means
of TIOR.
cycle in the TGR selected
in [2].
1 to start the counter
operation.
REJ09B0243-0500