DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 373
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Pin initialization procedures are described below for the numbered combinations in table 9.59. The
active level is assumed to be low.
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted
in Normal Mode: Figure 9.124 shows an explanatory diagram of the case where an error occurs
in normal mode and operation is restarted in normal mode after re-setting.
MTU2 module output
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The count operation is stopped by TSTR.
11. Not necessary when restarting in normal mode.
12. Initialize the pins with TIOR.
13. Set MTU2 output with the PFC.
14. Operation is restarted by TSTR.
After a reset, MTU2 output is low and ports are in the high-impedance state.
After a reset, the TMDR setting is for normal mode.
For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence.)
Set MTU2 output with the PFC.
The count operation is started by TSTR.
Output goes low on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
Port output
n = 0 to 15
Figure 9.124 Error Occurrence in Normal Mode, Recovery in Normal Mode
TIOC*A
TIOC*B
PEn
PEn
RESET
1
(normal)
TMDR
2
High-Z
High-Z
TOER
(1)
3
0 out)
TIOR
(1 init
4
(MTU2)
PFC
5
TSTR
(1)
6
Match
7
occurs
Error
8
Rev. 5.00 Mar. 06, 2009 Page 353 of 770
(PORT)
PFC
9
TSTR
(0)
10
(normal)
TMDR
11
0 out)
TIOR
(1 init
12
REJ09B0243-0500
(MTU2)
PFC
13
TSTR
(1)
14
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