DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 150
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 150 of 794
- Download datasheet (5Mb)
Rev. 5.00 Mar. 06, 2009 Page 130 of 770
REJ09B0243-0500
Bit
18
17
16
15
14
13
Bit Name
⎯
UBIDA
⎯
SCMFCA
SCMFCB
SCMFDA
Initial
Value
0
0
0
0
0
0
R/W
R
R/W
R
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
User Break Disable A
Enables or disables the user break interrupt request
when the channel A break conditions are satisfied.
0: User break interrupt request is enabled when break
1: User break interrupt request is disabled when break
Reserved
This bit is always read as 0. The write value should
always be 0.
L Bus Cycle Condition Match Flag A
When the L bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not
1: The L bus cycle condition for channel A matches
L Bus Cycle Condition Match Flag B
When the L bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not
1: The L bus cycle condition for channel B matches
I Bus Cycle Condition Match Flag A
When the I bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel A does not
1: The I bus cycle condition for channel A matches
conditions are satisfied
conditions are satisfied
match
match
match
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