DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 312

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 5.00 Mar. 06, 2009 Page 292 of 770
REJ09B0243-0500
Figure 9.57 Example of Procedure for Setting Output Waveform Control at Synchronous
⎯ Example of Procedure for Setting Output Waveform Control at Synchronous Counter
⎯ Examples of Output Waveform Control at Synchronous Counter Clearing in
Clearing in Complementary PWM Mode
An example of the procedure for setting output waveform control at synchronous counter
clearing in complementary PWM mode is shown in figure 9.57.
Complementary PWM Mode
Figures 9.58 to 9.61 show examples of output waveform control in which the MTU2
operates in complementary PWM mode and synchronous counter clearing is generated
while the WRE bit in TWCR is set to 1. In the examples shown in figures 9.58 to 9.61,
synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 9.56,
respectively.
synchronous counter clearing
synchronous counter clearing
complementary PWM mode
Output waveform control at
Output waveform control at
Start count operation
Stop count operation
Set TWCR and
Counter Clearing in Complementary PWM Mode
[1]
[2]
[3]
[1] Clear bits CST3 and CST4 in the timer
[2] Read bit WRE in TWCR and then write 1
[3] Set bits CST3 and CST4 in TSTR to 1 to
start register (TSTR) to 0, and halt timer
counter (TCNT) operation. Perform
TWCR setting while TCNT_3 and
TCNT_4 are stopped.
to it to suppress initial value output at
counter clearing.
start count operation.