DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 428

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 5.00 Mar. 06, 2009 Page 408 of 770
REJ09B0243-0500
Bit
5
4
3
2 to 0
Bit Name
RSTS
WOVF
IOVF
CKS[2:0]
Initial
Value
0
0
0
000
R/W
R/W
R/W
R/W
R/W
Description
Reset Select
Selects the type of reset when the WTCNT overflows in
watchdog timer mode. In interval timer mode, this setting
is ignored.
0: Power-on reset
1: Manual reset
Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in watchdog
timer mode. This bit is not set in interval timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
Interval Timer Overflow
Indicates that the WTCNT has overflowed in interval timer
mode. This bit is not set in watchdog timer mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
Clock Select 2 to 0
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is shown
inside the parenthesis in the table is the value when the
peripheral clock (Pφ) is 40 MHz.
000: Pφ (6.4 μs)
001: Pφ /4 (25.6 μs)
010: Pφ /16 (102.4 μs)
011: Pφ /32 (204.8 μs)
100: Pφ /64 (409.6 μs)
101: Pφ /256 (1.64 ms)
110: Pφ /1024 (6.55 ms)
111: Pφ /4096 (26.21 ms)
Note: If bits CKS2 to CKS0 are modified when the WDT
is operating, the up-count may not be performed
correctly. Ensure that these bits are modified only
when the WDT is not operating.

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