82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 96

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

6.2.8
OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration
OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration
Programming Information
IDT82V3352
Address: 6DH
Type: Read / Write
Default Value: 00001000
Address:71H
Type: Read / Write
Default Value: 00001000
OUT2_PATH_S
OUT1_PATH_S
7 - 4
3 - 0
7 - 4
3 - 0
Bit
Bit
EL3
EL3
7
7
OUTPUT CONFIGURATION REGISTERS
OUT1_PATH_SEL[3:0]
OUT2_PATH_SEL[3:0]
OUT1_DIVIDER[3:0]
OUT2_DIVIDER[3:0]
OUT2_PATH_S
OUT1_PATH_S
Name
Name
EL2
EL2
6
6
These bits select an input to OUT1.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100 ~ 1111: Reserved.
These bits select a division factor of the divider for OUT1.
The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output
(selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0 DPLL outputs, please
refer to
Table 21~Table 22
OUT2_PATH_S
These bits select an input to OUT2.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100 ~ 1111: Reserved.
These bits select a division factor of the divider for OUT2.
The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output
(selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0 DPLL outputs, please
refer to
Table 21~Table 22
OUT1_PATH_S
EL1
EL1
5
5
Table 20
Table 20
for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
for the division factor selection.
for the division factor selection.
OUT2_PATH_S
OUT1_PATH_S
EL0
EL0
4
4
96
OUT2_DIVIDER
OUT1_DIVIDER
3
3
3
3
Description
Description
OUT2_DIVIDER
OUT1_DIVIDER
2
2
2
2
SYNCHRONOUS ETHERNET WAN PLL
OUT2_DIVIDER
OUT1_DIVIDER
1
1
1
1
OUT2_DIVIDER
OUT1_DIVIDER
March 23, 2009
0
0
0
0