82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 15

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 2: Related Bit / Register in Chapter 3.2
3
3.1
default value or status.
50 µs. After the RST pin is pulled high, the device will still be in reset
state for 500 ms (typical). If the RST pin is held low continuously, the
device remains in reset state.
Functional Description
IDT82V3352
The reset operation resets all registers and state machines to their
After power on, the device must be reset for normal operation.
For a complete reset, the RST pin must be asserted low for at least
NOMINAL_FREQ_VALUE[23:0]
FUNCTIONAL DESCRIPTION
RESET
OSC_EDGE
Bit
NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
15
3.2
input on the OSCI pin. This clock is provided for the device as a master
clock. The master clock is used as a reference clock for all the internal
circuits. A better active edge of the master clock is selected by the
OSC_EDGE bit to improve jitter and wander performance.
pin.
NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within
±741 ppm.
GR-253-CORE, ITU-T G.812 and G.813 criteria.
A nominal 12.8000 MHz clock, provided by a crystal oscillator, is
In fact, an offset from the nominal frequency may input on the OSCI
The performance of the master clock should meet GR-1244-CORE,
Register
This
MASTER CLOCK
offset
can
SYNCHRONOUS ETHERNET WAN PLL
be
compensated
by
March 23, 2009
Address (Hex)
setting
06, 05, 04
0A
the