82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 16

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

3.3
3.3.1
lowing technologies:
supported:
clock sources can be from T1, T2 or T3.
automatically detect whether the signal is PECL or LVDS. The clock
sources can be from T1, T2 or T3.
Functional Description
IDT82V3352
Altogether 5 clocks and 3 frame sync signals are input to the device.
The device provides 5 input clock ports.
According to the input port technology, the input ports support the fol-
According to the input clock source, the following clock sources are
IN1_CMOS ~ IN3_CMOS support CMOS input signal only and the
IN1_DIFF and IN2_DIFF support PECL/LVDS input signal only and
• PECL/LVDS
• CMOS
• T1: Recovered clock from STM-N or OC-n
• T2: PDH network synchronization timing
• T3: External synchronization reference timing
INPUT CLOCKS & FRAME SYNC SIGNALS
INPUT CLOCKS
16
Table 3: Related Bit / Register in Chapter 3.3
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
3.3.2
EX_SYNC1 to EX_SYNC3 pins respectively. They are CMOS inputs.
The input frequency should match the setting in the SYNC_FREQ[1:0]
bits.
output signal synchronization. Refer to
Output Signals
SYNC_FREQ[1:0]
IN_SONET_SDH
For SDH and SONET networks, the default frequency is different.
Three 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the
Only one of the three frame sync input signals is used for frame sync
Bit
FRAME SYNC INPUT SIGNALS
for details.
SYNCHRONOUS ETHERNET WAN PLL
INPUT_MODE_CNFG
Register
Chapter 3.13.2 Frame SYNC
March 23, 2009
Address (Hex)
09