82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 17

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 4: Related Bit / Register in Chapter 3.4
3.4
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz. For each input clock, the
DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
available for IN1_DIFF and IN2_DIFF), a DivN Divider and a Lock 8k
Divider, as shown in
should be used when the input clock is higher than (>) 155.52 MHz. The
input clock can be divided by 4, 5 or can bypass the HF Divider, as
determined by the IN1_DIFF_DIV[1:0]/IN2_DIFF_DIV[1:0] bits corre-
spondingly.
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
observe the following order:
Functional Description
IDT82V3352
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
Each Pre-Divider consists of a HF (High Frequency) Divider (only
The HF Divider, which is only available for IN1_DIFF and IN2_DIFF,
Either the DivN Divider or the Lock 8k Divider can be used or both
When the DivN Divider is used, the division factor setting should
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
PRE_DIVN_VALUE[14:8] bits.
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
INPUT CLOCK PRE-DIVIDER
input clock
IN_2K_4K_8K_INV
IN1_DIFF_DIV[1:0]
IN2_DIFF_DIV[1:0]
IN_FREQ[3:0]
DIRECT_DIV
LOCK_8K
Bit
Figure
Pre-Divider
3.
(for IN1_DIFF &
IN1_DIFF_DIV[1:0] bits / IN2_DIFF_DIV[1:0] bits
IN2_DIFF only)
HF Divider
Figure 3. Pre-Divider for An Input Clock
IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG, IN2_DIFF_CNFG,
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
DivN Divider
IN1_DIFF_IN2_DIFF_HF_DIV_CNFG
17
FR_MFR_SYNC_CNFG
PRE_DIV_CH_CNFG
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
lower than (<) 155.52 MHz.
8 kHz automatically.
on the input clock on one of the clock input pin and the DPLL required
clock. Here is an example:
required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of
register IN2_DIFF to ‘0010’. Do the following step by step to divide the
input clock:
DIRECT_DIV bit
IN3_CNFG
Once the division factor is set for the input clock selected by the
The DivN Divider can only divide the input clock whose frequency is
When the Lock 8k Divider is used, the input clock is divided down to
The Pre-Divider configuration and the division factor setting depend
The input clock on the IN2_DIFF pin is 622.08 MHz; the DPLL
Register
1. Use the HF Divider to divide the clock down to 155.52 MHz:
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
622.08 ÷ 155.52 = 4, so set the IN2_DIFF_DIV[1:0] bits to ‘01’;
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN2_DIFF_CNFG to ‘1’ and
the LOCK_8K bit in Register IN2_DIFF_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Lock 8k Divider
SYNCHRONOUS ETHERNET WAN PLL
LOCK_8K bit
DPLL required clock
16, 17, 19, 1A, 1D
Address (Hex)
March 23, 2009
25, 24
74
23
18