82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 83

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

6.2.6
OPERATING_STS - DPLL Operating Status
Programming Information
IDT82V3352
Address: 52H
Type: Read
Default Value: 10000001
EX_SYNC_ALA
2 - 0
Bit
RM_MON
7
6
5
4
3
7
T0 DPLL STATE MACHINE CONTROL REGISTERS
T0_DPLL_OPERATING_MODE[2:0]
T0_DPLL_SOFT_FREQ_ALARM
EX_SYNC_ALARM_MON
T0_DPLL_LOCK
6
-
Name
-
-
T0_DPLL_SOFT
_FREQ_ALARM
5
This bit indicates whether the selected frame sync input signal is in external sync alarm status.
0: No external sync alarm.
1: In external sync alarm status. (default)
Reserved.
This bit indicates whether the T0 DPLL is in soft alarm status.
0: No T0 DPLL soft alarm. (default)
1: In T0 DPLL soft alarm status.
Reserved.
This bit indicates the T0 DPLL locking status.
0: Unlocked. (default)
1: Locked.
These bits indicate the current operating mode of T0 DPLL.
000: Reserved.
001: Free-Run. (default)
010: Holdover.
011: Reserved.
100: Locked.
101: Pre-Locked2.
110: Pre-Locked.
111: Lost-Phase.
4
-
83
T0_DPLL_LO
CK
3
T0_DPLL_OPER
ATING_MODE2
Description
2
SYNCHRONOUS ETHERNET WAN PLL
T0_DPLL_OPER
ATING_MODE1
1
T0_DPLL_OPER
ATING_MODE0
March 23, 2009
0