82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 44

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 30: Register List and Map (Continued)
Programming Information
IDT82V3352
Address
(Hex)
3A
3B
3C
3D
3E
31
32
33
34
35
36
37
38
39
3F
40
41
42
44
UPPER_THRESHOLD_0_CNFG
Upper Threshold for Leaky Bucket
Configuration 0
LOWER_THRESHOLD_0_CNFG
Lower Threshold for Leaky Bucket
Configuration 0
BUCKET_SIZE_0_CNFG - Bucket
Size for Leaky Bucket Configuration 0
DECAY_RATE_0_CNFG - Decay Rate
for Leaky Bucket Configuration 0
UPPER_THRESHOLD_1_CNFG
Upper Threshold for Leaky Bucket
Configuration 1
LOWER_THRESHOLD_1_CNFG
Lower Threshold for Leaky Bucket
Configuration 1
BUCKET_SIZE_1_CNFG - Bucket
Size for Leaky Bucket Configuration 1
DECAY_RATE_1_CNFG - Decay Rate
for Leaky Bucket Configuration 1
UPPER_THRESHOLD_2_CNFG
Upper Threshold for Leaky Bucket
Configuration 2
LOWER_THRESHOLD_2_CNFG
Lower Threshold for Leaky Bucket
Configuration 2
BUCKET_SIZE_2_CNFG - Bucket
Size for Leaky Bucket Configuration 2
DECAY_RATE_2_CNFG - Decay Rate
for Leaky Bucket Configuration 2
UPPER_THRESHOLD_3_CNFG
Upper Threshold for Leaky Bucket
Configuration 3
LOWER_THRESHOLD_3_CNFG
Lower Threshold for Leaky Bucket
Configuration 3
BUCKET_SIZE_3_CNFG - Bucket
Size for Leaky Bucket Configuration 3
DECAY_RATE_3_CNFG - Decay Rate
for Leaky Bucket Configuration 3
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
IN1_IN2_CMOS_STS - CMOS Input
Clock 1 & 2 Status
Register Name
-
-
-
-
-
-
-
-
Bit 7
-
-
-
-
-
-
IN2_CMOS
_FREQ_H
ARD_ALA
Bit 6
RM
-
-
-
-
-
IN2_CMOS
_NO_ACTI
VITY_ALA
Bit 5
RM
44
-
-
-
-
-
LOWER_THRESHOLD_0_DATA[7:0]
LOWER_THRESHOLD_1_DATA[7:0]
LOWER_THRESHOLD_2_DATA[7:0]
LOWER_THRESHOLD_3_DATA[7:0]
UPPER_THRESHOLD_0_DATA[7:0]
UPPER_THRESHOLD_1_DATA[7:0]
UPPER_THRESHOLD_2_DATA[7:0]
UPPER_THRESHOLD_3_DATA[7:0]
BUCKET_SIZE_0_DATA[7:0]
BUCKET_SIZE_1_DATA[7:0]
BUCKET_SIZE_2_DATA[7:0]
BUCKET_SIZE_3_DATA[7:0]
IN2_CMOS
K_ALARM
_PH_LOC
IN_FREQ_VALUE[7:0]
Bit 4
-
-
-
-
-
Bit 3
-
-
-
-
-
IN_FREQ_READ_CH[3:0]
IN1_CMOS
SYNCHRONOUS ETHERNET WAN PLL
_FREQ_H
ARD_ALA
Bit 2
RM
-
-
-
-
IN1_CMOS
DECAY_RATE_0_DATA
DECAY_RATE_1_DATA
DECAY_RATE_2_DATA
DECAY_RATE_3_DATA
_NO_ACTI
VITY_ALA
Bit 1
RM
[1:0]
[1:0]
[1:0]
[1:0]
IN1_CMOS
K_ALARM
_PH_LOC
Bit 0
March 23, 2009
Reference
Page
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P 72
P 72
P 72
P 73
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P 73
P 74
P 74
P 74
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P 75
P 76
P 77