82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 55

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

INTERRUPTS2_STS - Interrupt Status 2
INTERRUPTS3_STS - Interrupt Status 3
Programming Information
IDT82V3352
Address: 0EH
Type: Read / Write
Default Value: 00XXXXX1
Address: 0FH
Type: Read / Write
Default Value: 11X1XXXX
EX_SYNC_ALARM
T0_OPERATING
5 - 1
6-0
Bit
Bit
7
7
6
0
_MODE
7
7
EX_SYNC_ALARM
T0_OPERATING_MODE
T0_MAIN_REF_FAILED
Name
IN3_CMOS
T0_MAIN_REF_F
-
Name
-
AILED
6
6
-
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn_CMOS / INn_DIFF
bit (4AH, 4BH).
0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for IN3_CMOS for T0 path, i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding IN3_CMOS bit (b0, 4BH).
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
5
-
5
-
4
-
4
-
55
3
3
-
-
Description
Description
2
2
-
-
SYNCHRONOUS ETHERNET WAN PLL
1
-
1
-
March 23, 2009
IN3_CMOS
0
0
-