82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 36

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 26: Related Bit / Register in Chapter 3.14
3.14
interrupt status bit. If the corresponding interrupt enable bit is set, any of
the interrupts can be reported by the INT_REQ pin. The output charac-
teristics on the INT_REQ pin are determined by the HZ_EN bit and the
INT_POL bit.
interrupt status bit. The INT_REQ pin will be inactive only when all the
pending enabled interrupts are cleared.
reported by the TDO pin, as determined by the LOS_FLAG_TO_TDO
bit.
Functional Description
IDT82V3352
The interrupt sources of the device are as follows:
All of the above interrupt events are indicated by the corresponding
Interrupt events are cleared by writing a ‘1’ to the corresponding
In addition, the interrupt of T0 selected input clock fail can be
LOS_FLAG_TO_TDO
• Input clocks for T0 path validity change
• T0 selected input clock fail
• T0 DPLL operating mode switch
• External sync alarm
INT_POL
HZ_EN
INTERRUPT SUMMARY
Bit
MON_SW_PBO_CNFG
INTERRUPT_CNFG
Register
Address (Hex)
0C
0B
36
3.15
The main features supported by the T0 path are as follows:
• Phase lock alarm;
• Forced or Automatic input clock selection/switch;
• 3 primary and 3 secondary, temporary DPLL operating modes,
• Automatic switch between starting, acquisition and locked band-
• Programmable DPLL bandwidths from 0.1 Hz to 560 Hz in 11
• Programmable damping factors: 1.2, 2.5, 5, 10 and 20;
• Fast loss, coarse phase loss, fine phase loss and hard limit
• Output phase and frequency offset limited;
• Automatic Instantaneous, Automatic Slow Averaged, Automatic
• PBO to minimize output phase transients;
• Programmable output phase offset;
• Low jitter multiple clock outputs with programmable polarity;
• Low jitter 2 kHz and 8 kHz frame sync signal outputs with pro-
switched automatically or under external control;
widths/damping factors;
steps;
exceeding monitoring;
Fast Averaged or Manual holdover frequency offset acquiring;
grammable pulse width and polarity.
T0 SUMMARY
SYNCHRONOUS ETHERNET WAN PLL
March 23, 2009