82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 102

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

SYNC_PHASE_CNFG - Sync Phase Configuration
Programming Information
IDT82V3352
Address:7DH
Type: Read / Write
Default Value: XX000000
7 - 6
5 - 4
3 - 2
1 - 0
Bit
7
-
SYNC_PH3[1:0]
SYNC_PH2[1:0]
SYNC_PH1[1:0]
Name
-
6
-
Reserved.
These bits set the sampling of EX_SYNC3 when EX_SYNC3 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC3 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
These bits set the sampling of EX_SYNC2 when EX_SYNC2 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC2 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
SYNC_PH31
5
SYNC_PH30
4
102
SYNC_PH21
3
Description
SYNC_PH20
2
SYNCHRONOUS ETHERNET WAN PLL
SYNC_PH11
1
March 23, 2009
SYNC_PH10
0