82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 8

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

DESCRIPTION
chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network appli-
cations.
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
Locked and Holdover. In Free-Run mode, the DPLL refers to the master
clock. In Locked mode, the DPLL locks to the selected input clock. In
Holdover mode, the DPLL resorts to the frequency data acquired in
Locked mode. Whatever the operating mode is, the DPLL gives a stable
performance without being affected by operating conditions or silicon
process variations.
Description
IDT82V3352
The IDT82V3352 is an integrated, single-chip solution for the Syn-
The device supports three types of input clock sources: recovered
The T0 path supports three primary operating modes: Free-Run,
8
device will be in a better jitter/wander performance.
Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set-
tings cover all SONET / SDH clock synchronization requirements.
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
cessor interface. The device supports Serial microprocessor interface
mode only.
tion.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
The device provides programmable DPLL bandwidths: 0.1 Hz to 560
A high stable input is required for the master clock in different appli-
All the read/write registers are accessed through a serial micropro-
The device can be used typically in
SYNCHRONOUS ETHERNET WAN PLL
Chapter 3.17 Line Card Applica-
March 23, 2009