82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 100

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2
Programming Information
IDT82V3352
Address:7BH
Type: Read / Write
Default Value: 0XXXXX00
PH_OFFSET_E
6 - 2
1 - 0
Bit
7
N
7
PH_OFFSET_EN
PH_OFFSET[9:8]
Name
-
6
-
This bit determines whether the input-to-output phase offset is enabled.
0: Disabled. (default)
1: Enabled.
Reserved.
These bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the input-to-output phase offset in ns
to adjust will be gotten.
5
-
4
-
100
3
-
Description
2
-
SYNCHRONOUS ETHERNET WAN PLL
PH_OFFSET9
1
PH_OFFSET8
March 23, 2009
0