82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 49

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Programming Information
IDT82V3352
Address: 08H
Type: Read / Write
Default Value: 00110010
MULTI_FACTO
7 - 6
5 - 0
Bit
R1
7
TIME_OUT_VALUE[5:0]
MULTI_FACTOR[1:0]
MULTI_FACTO
Name
R0
6
TIME_OUT_VA
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
00: 2 (default)
01: 4
10: 8
11: 16
These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the
alarm is raised).
LUE5
5
TIME_OUT_VA
LUE4
4
49
TIME_OUT_VA
LUE3
3
Description
TIME_OUT_VA
LUE2
2
SYNCHRONOUS ETHERNET WAN PLL
TIME_OUT_VA
LUE1
1
TIME_OUT_VAL
March 23, 2009
UE0
0