82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 60

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

IN1_IN2_DIFF_HF_DIV_CNFG - Differential Input Clock 1 & 2 High Frequency Divider Configuration
Programming Information
IDT82V3352
Address: 18H
Type: Read / Write
Default Value: 00XXXX00
IN2_DIFF_DIV1
7 - 6
5 - 2
1 - 0
Bit
7
IN2_DIFF_DIV[1:0]
IN1_DIFF_DIV[1:0]
IN2_DIFF_DIV0
Name
-
6
These bits determine whether the HF Divider is used and what the division factor is for IN2_DIFF frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
Reserved.
These bits determine whether the HF Divider is used and what the division factor is for IN1_DIFF frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
5
-
4
-
60
3
-
Description
2
-
SYNCHRONOUS ETHERNET WAN PLL
IN1_DIFF_DIV1
1
IN1_DIFF_DIV0
March 23, 2009
0