82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 43

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 30: Register List and Map (Continued)
Programming Information
IDT82V3352
Address
(Hex)
0D
0E
1A
1D
2A
2E
0F
10
12
16
17
18
19
23
24
25
27
28
2F
11
INTERRUPTS1_STS - Interrupt Status
1
INTERRUPTS2_STS - Interrupt Status
2
INTERRUPTS3_STS - Interrupt Status
3
INTERRUPTS1_ENABLE_CNFG
Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG
Interrupt Control 2
INTERRUPTS3_ENABLE_CNFG
Interrupt Control 3
IN1_CMOS_CNFG - CMOS Input
Clock 1 Configuration
IN2_CMOS_CNFG - CMOS Input
Clock 2 Configuration
IN1_IN2_DIFF_HF_DIV_CNFG - Dif-
ferential Input Clock 1 & 2 High Fre-
quency Divider Configuration
IN1_DIFF_CNFG - Differential Input
Clock 1 Configuration
IN2_DIFF_CNFG - Differential Input
Clock 2 Configuration
IN3_CMOS_CNFG - CMOS Input
Clock 3 Configuration
PRE_DIV_CH_CNFG - DivN Divider
Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider
Division Factor Configuration 1
PRE_DIVN[14:8]_CNFG
Divider Division Factor Configuration 2
IN1_IN2_CMOS_SEL_PRIORITY_CN
FG - CMOS Input Clock 1 & 2 Priority
Configuration *
IN1_IN2_DIFF_SEL_PRIORITY_CNF
G - Differential Input Clock 1 & 2 Prior-
ity Configuration *
IN3_CMOS_SEL_PRIORITY_CNFG -
CMOS Input Clock 3 Priority Configu-
ration *
FREQ_MON_FACTOR_CNFG - Fac-
tor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CN
FG - Frequency Monitor Threshold for
All Input Clocks Configuration
Register Name
-
DivN
Input Clock Quality Monitoring Configuration & Status Registers
-
-
-
ATING_MO
ATING_MO
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
T0_OPER
EX_SYNC
T0_OPER
EX_SYNC
Input Clock Frequency & Priority Configuration Registers
_ALARM
_ALARM
IN2_DIFF_DIV[1:0]
Bit 7
DE
DE
IV
IV
IV
IV
IV
-
-
-
-
-
-
-
IN2_CMOS_SEL_PRIORITY[3:0]
IN2_DIFF_SEL_PRIORITY[3:0]
T0_MAIN_
T0_MAIN_
REF_FAIL
REF_FAIL
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
Bit 6
ED
ED
-
-
-
-
-
-
-
-
IN2_DIFF
IN2_DIFF
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
Bit 5
43
-
-
-
-
-
-
-
-
-
PRE_DIVN_VALUE[7:0]
IN1_DIFF IN2_CMOS IN1_CMOS
IN1_DIFF IN2_CMOS IN1_CMOS
Bit 4
-
-
-
-
-
-
-
-
-
PRE_DIVN_VALUE[14:8]
Bit 3
-
-
-
-
-
ALL_FREQ_HARD_THRESHOLD[3:0]
IN1_CMOS_SEL_PRIORITY[3:0]
IN3_CMOS_SEL_PRIORITY[3:0]
IN1_DIFF_SEL_PRIORITY[3:0]
FREQ_MON_FACTOR[3:0]
PRE_DIV_CH_VALUE[3:0]
SYNCHRONOUS ETHERNET WAN PLL
Bit 2
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
-
-
-
-
-
IN1_DIFF_DIV[1:0]
Bit 1
-
-
-
-
-
-
IN3_CMOS
IN3_CMOS
Bit 0
March 23, 2009
-
-
-
-
Reference
Page
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