82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 75

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3
IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection
Programming Information
IDT82V3352
Address: 40H
Type: Read / Write
Default Value: XXXXXX01
Address: 41H
Type: Read / Write
Default Value: XXXX0000
7 - 2
1 - 0
Bit
7 - 4
3 - 0
Bit
7
-
7
-
DECAY_RATE_3_DATA[1:0]
IN_FREQ_READ_CH[3:0]
Name
Name
6
-
-
-
6
-
Reserved.
These bits select an input clock, the frequency of which with respect to the reference clock can be read.
0000: Reserved. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
Reserved.
These bits set a decay rate for the internal leaky bucket accumulator:
00: The accumulator decreases by 1 in every 128 ms with no event detected.
01: The accumulator decreases by 1 in every 256 ms with no event detected. (default)
10: The accumulator decreases by 1 in every 512 ms with no event detected.
11: The accumulator decreases by 1 in every 1024 ms with no event detected.
5
-
5
-
4
-
4
-
IN_FREQ_READ
75
_CH3
3
3
-
Description
Description
IN_FREQ_READ
_CH2
2
2
-
SYNCHRONOUS ETHERNET WAN PLL
IN_FREQ_READ
DECAY_RATE_
_CH1
3_DATA1
1
1
IN_FREQ_READ
DECAY_RATE_
March 23, 2009
3_DATA0
_CH0
0
0