82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 23

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 12: Related Bit / Register in Chapter 3.7
DPLL locking.
Functional Description
IDT82V3352
The selected input clock with a phase lock alarm is disqualified for T0
• Be cleared when a ‘1’ is written to the corresponding
• Be cleared after the period (= TIME_OUT_VALUE[5:0] X
INn_CMOS_PH_LOCK_ALARM
ALARM bit;
MULTI_FACTOR[1:0] in second) which starts from when the
alarm is raised.
INn_CMOS_PH_LOCK_ALARM (n = 1, 2, or 3)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
T0_DPLL_SOFT_FREQ_ALARM
DPLL_FREQ_HARD_LIMT[15:0]
DPLL_FREQ_SOFT_LIMT[6:0]
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
PH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
TIME_OUT_VALUE[5:0]
PH_ALARM_TIMEOUT
FREQ_LIMT_PH_LOS
MULTI_FACTOR[1:0]
T0_DPLL_LOCK
FAST_LOS_SW
WIDE_EN
Bit
/
INn_DIFF_PH_LOCK_
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
PHASE_LOSS_COARSE_LIMIT_CNFG
IN1_IN2_CMOS_STS, IN3_CMOS_STS
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
23
PHASE_ALARM_TIME_OUT_CNFG
PHASE_LOSS_FINE_LIMIT_CNFG
DPLL_FREQ_SOFT_LIMIT_CNFG
INPUT_MODE_CNFG
IN1_IN2_DIFF_STS
OPERATING_STS
Register
SYNCHRONOUS ETHERNET WAN PLL
Address (Hex)
March 23, 2009
67, 66
44, 47
5B *
5A *
52
65
08
45
09