82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 33

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Functional Description
Table 22: Outputs on OUT1 & OUT2 if Derived from T4 APLL
IDT82V3352
Note:
1. n = 1 or 2. Each output is assigned a frequency divider.
2. In the APLL, the selected T0 DPLL output may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is
reserved.
3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT1.
OUTn_DIVIDER[3
:0] (Output
Divider)
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
1
77.76 MHz X 4 12E1 X 4 16E1 X 4 24T1 X 4 16T1 X 4
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
51.84 MHz
38.88 MHz
25.92 MHz
19.44 MHz
6.48 MHz
3
3
48E1
24E1
12E1
8E1
6E1
4E1
3E1
2E1
E1
64E1
32E1
16E1
8E1
4E1
2E1
E1
outputs on
96T1
48T1
24T1
16T1
12T1
8T1
6T1
4T1
3T1
2T1
T1
OUT1 & OUT2
64T1
32T1
16T1
8T1
4T1
2T1
T1
Output is disabled (output high).
Output is disabled (output low).
33
E3
E3
if derived from T4 APLL output
T3
T3
(26 MHz X 2)
52 MHz
26 MHz
13 MHz
GSM
SYNCHRONOUS ETHERNET WAN PLL
156.25 MHz
312.5 MHz
62.5 MHz
125 MHz
25 MHz
5 MHz
ETH
2
(30.72 MHz X 10)
153.6 MHz
76.8 MHz
38.4 MHz
OBSAI
March 23, 2009
(40 MHz)
20 MHz
10 MHz
5 MHz
GPS