82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 92

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3
DPLL_APLL_PATH_CNFG - DPLL & APLL Path Configuration
Programming Information
Address: 5EH
Type: Read / Write
Default Value: 00000000
IDT82V3352
Address: 5FH
Type: Read / Write
Default Value: 00000000
Address: 60H
Type: Read / Write
Default Value: 01000X0X
T0_HOLDOVER
T0_HOLDOVER
T4_APLL_PATH
7 - 4
3 -0
_FREQ15
7 - 0
_FREQ23
Bit
7 - 0
Bit
Bit
7
7
7
3
T0_HOLDOVER_FREQ[23:16]
T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
T0_HOLDOVER
T0_HOLDOVER
T4_APLL_PA
T4_APLL_PATH[3:0]
_FREQ14
_FREQ22
TH2
6
Name
Name
6
6
Name
-
T4_APLL_PA
T0_HOLDOVER
T0_HOLDOVER
TH1
_FREQ13
_FREQ21
5
The T0_HOLDOVER_FREQ[23:0] bits represent a 2’s complement signed integer.
In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manu-
ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast aver-
aged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH).
5
5
These bits select an input to the T4 APLL.
0000: The output of T0 DPLL 77.76 MHz path.
0001: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0010: The output of T0 DPLL 16E1/16T1 path.
0011: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path.
0100~1XXX: Reserved.
Reserved.
T4_APLL_PA
TH0
T0_HOLDOVE
T0_HOLDOVE
4
R_FREQ12
R_FREQ20
4
4
92
T0_HOLDOVE
T0_HOLDOVE
3
-
R_FREQ11
R_FREQ19
3
3
Description
Description
Description
T0_HOLDOVE
T0_HOLDOVE
R_FREQ10
R_FREQ18
2
-
2
2
SYNCHRONOUS ETHERNET WAN PLL
T0_HOLDOVE
T0_HOLDOVE
R_FREQ17
R_FREQ9
1
-
1
1
T0_HOLDOVE
T0_HOLDOVE
March 23, 2009
R_FREQ16
R_FREQ8
0
-
0
0