82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 19

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 5: Related Bit / Register in Chapter 3.5
3.5.2
ence clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
status
INn_CMOS_FREQ_HARD_ALARM bit (n = 1, 2 or 3) /
INn_DIFF_FREQ_HARD_ALARM bit (n = 1 or 2). When the
FREQ_MON_HARD_EN bit is ‘0’, no frequency hard alarm is raised
even if the input clock is above the frequency hard alarm threshold.
Functional Description
IDT82V3352
INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2, or 3)
Frequency is monitored by comparing the input clock with a refer-
A frequency hard alarm threshold is set for frequency monitoring. If
The frequency hard alarm threshold can be calculated as follows:
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3)
LOWER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0)
UPPER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0)
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2)
INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2)
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
BUCKET_SIZE_n_DATA[7:0] (3 ≥ n ≥ 0)
DECAY_RATE_n_DATA[1:0] (3 ≥ n ≥ 0)
ALL_FREQ_HARD_THRESHOLD[3:0]
of
FREQUENCY MONITORING
FREQ_MON_FACTOR[3:0]
IN_FREQ_READ_CH[3:0]
FREQ_MON_HARD_EN
IN_FREQ_VALUE[7:0]
IN_NOISE_WINDOW
the
BUCKET_SEL[1:0]
FREQ_MON_CLK
input
Bit
clock
is
indicated
LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG
UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG
IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG,
by
BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG
DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG
the
ALL_FREQ_MON_THRESHOLD_CNFG
IN1_IN2_CMOS_STS, IN3_CMOS_STS
IN2_DIFF_CNFG, IN3_CMOS_CNFG
19
FREQ_MON_FACTOR_CNFG
IN_FREQ_READ_CH_CNFG
PHASE_MON_PBO_CNFG
MON_SW_PBO_CNFG
selection for T0 DPLL.
with respect to the reference clock are monitored. If any edge drifts out-
side ±5%, the input clock is disqualified for clock selection for T0 DPLL.
The input clock is qualified if any edge drifts inside ±5%. This function is
supported only when the IN_NOISE_WINDOW bit is ‘1’.
can be read by doing the following step by step:
depends on the application.
IN_FREQ_READ_STS
IN1_IN2_DIFF_STS
The input clock with a frequency hard alarm is disqualified for clock
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
The frequency of each input clock with respect to the reference clock
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
Register
as follows:
bits;
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X
FREQ_MON_FACTOR[3:0]
SYNCHRONOUS ETHERNET WAN PLL
16, 17, 19, 1A, 1D
Address (Hex)
33, 37, 3B, 3F
31, 35, 39, 3D
32, 36, 3A, 3E
34, 38, 3C, 40
March 23, 2009
44, 47
0B
2F
2E
45
78
41
42