82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 24

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

3.8
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection
any time. In this case, whether the input clock is qualified for DPLL lock-
ing does not affect the clock switch.
clock switch depends on its validity and priority. If the current selected
input clock is disqualified, a new qualified input clock may be switched
to.
3.8.1
clock quality monitoring (refer to
toring). When all of the following conditions are satisfied, the input clock
is valid; otherwise, it is invalid.
lowing conditions are satisfied; otherwise, it is invalid.
bit (n = 1, 2 or 3) / INn_DIFF
ity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), the
INn_CMOS
3
selected input clock changes from ‘valid’ to ‘invalid’, the
T0_MAIN_REF_FAILED
bit is ‘1’, an interrupt will be generated. This interrupt can also be indi-
cated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
3.8.2
the REVERTIVE_MODE bit.
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
Functional Description
IDT82V3352
bit is ‘1’, an interrupt will be generated.
If the input clock is selected by External Fast selection or by Forced
When the input clock is selected by Automatic selection, the input
For all the input clocks, the validity depends on the results of input
The T0 selected input clock is valid when all of the above and the fol-
The validities of all the input clocks are indicated by the INn_CMOS
When the T0 selected input clock has failed, i.e., the validity of the T0
Revertive and Non-Revertive switches are supported, as selected by
The difference between Revertive and Non-Revertive switches is
• No no-activity alarm (the INn_CMOS_NO_ACTIVITY_ALARM /
• No frequency hard alarm (the INn_CMOS_FREQ_HARD_
• If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
• No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM /
• If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
INn_DIFF_NO_ACTIVITY_ALARM bit is ‘0’);
ALARM / INn_DIFF_FREQ_HARD_ALARM bit is ‘0’);
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
INn_DIFF_PH_LOCK_ALARM bit is ‘0’;
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
SELECTED INPUT CLOCK SWITCH
INPUT CLOCK VALIDITY
SELECTED INPUT CLOCK SWITCH
2
/ INn_DIFF
1
2
bit will be set. If the T0_MAIN_REF_FAILED
bit will be set. If the INn_CMOS
1
bit (n = 1 or 2). When the input clock valid-
Chapter 3.5 Input Clock Quality Moni-
&
Chapter 3.6.2 Forced
3
/ INn_DIFF
Selection)
1
2
24
available for selection. In Non-Revertive switch, input clock switch is
minimized.
as shown in
Table 13: Conditions of Qualified Input Clocks Available for T0
Selection
satisfied.
3.8.2.1
another qualified input clock with a higher priority than the current
selected input clock is available.
fied:
switch. If more than one qualified input clock is available and has the
same priority, the input clock with the smallest ‘n’ is selected. See
Table 8
3.8.2.2
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected. See
each input clock.
3.8.3
CURRENTLY_SELECTED_INPUT[3:0] bits.
cated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_
PRIORITY_VALIDATED[3:0]
_VALIDATED[3:0] bits respectively. If more than one input clock has the
same priority, the input clock with the smallest ‘n’ is indicated by the
T0
Conditions of the qualified input clocks available for T0 selection are
The input clock is disqualified if any of the above conditions is not
In summary, the selected input clock can be switched by:
In Revertive switch, the selected input clock is switched when
The selected input clock is switched if any of the following is satis-
A qualified input clock with the highest priority is selected by revertive
In Non-Revertive switch, the T0 selected input clock is not switched
The
The qualified input clocks with the three highest priorities are indi-
• Valid, i.e., the INn_CMOS
• Priority
• External Fast selection;
• Forced selection;
• Revertive switch;
• Non-Revertive switch;
• the selected input clock is disqualified;
• another qualified input clock with a higher priority than the
_PRIORITY[3:0] / INn_DIFF_SEL_PRIORITY[3:0] bits are not ‘0000’
selected input clock is available.
Conditions of Qualified Input Clocks Available for T0 Selection
for the ‘n’ assigned to each input clock.
selected
Revertive Switch
Non-Revertive Switch
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
Table
enabled,
13:
input
SYNCHRONOUS ETHERNET WAN PLL
i.e.,
1
/ INn_DIFF
bits
clock
the
and
corresponding
1
Table 8
is
bit is ‘1’;
the
indicated
for the ‘n’ assigned to
THIRD_PRIORITY
March 23, 2009
INn_CMOS_SEL
by
the