82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 47

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82V3352EDG

Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Table 30: Register List and Map (Continued)
6.2
6.2.1
ID[7:0] - Device ID 1
ID[15:8] - Device ID 2
NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1
Programming Information
Address: 04H
Type: Read / Write
Default Value: 00000000
IDT82V3352
Address
Address: 00H
Type: Read
Default Value: 10001000
Address: 01H
Type: Read
Default Value: 00010001
7 - 0
(Hex)
Bit
7D
NOMINAL_FRE
7 - 0
7 - 0
Q_VALUE7
Bit
Bit
NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
ID15
ID7
SYNC_PHASE_CNFG - Sync Phase
Configuration
7
7
7
REGISTER DESCRIPTION
GLOBAL CONTROL REGISTERS
Name
Register Name
ID[15:8]
ID[7:0]
Name
Name
NOMINAL_FRE
Q_VALUE6
ID14
ID6
6
6
6
Refer to the description of the ID[15:8] bits (b7~0, 01H).
The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3352.
NOMINAL_FRE
Q_VALUE5
ID13
ID5
5
5
5
Bit 7
-
NOMINAL_FRE
Bit 6
Q_VALUE4
-
ID12
ID4
4
4
4
Bit 5
SYNC_PH3[1:0]
47
NOMINAL_FRE
Q_VALUE3
ID11
ID3
3
3
3
Bit 4
Description
Description
Description
NOMINAL_FRE
Bit 3
SYNC_PH2[1:0]
Q_VALUE2
ID10
ID2
2
2
2
SYNCHRONOUS ETHERNET WAN PLL
Bit 2
NOMINAL_FRE
Q_VALUE1
ID1
ID9
1
1
Bit 1
SYNC_PH1[1:0]
1
Bit 0
March 23, 2009
NOMINAL_FRE
Q_VALUE0
ID0
ID8
0
0
0
Reference
P 102
Page

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